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target/ppc: implement plxsd/pstxsd 

Implement instructions plxsd/pstxsd and port lxsd/stxsd to decode
tree.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-48-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Leandro Lupori 2022-03-02 06:51:38 +01:00 committed by Cédric Le Goater
parent 3909ff1fac
commit 7eec8cbb1b
4 changed files with 67 additions and 14 deletions
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2
target/ppc/insn32.decode
View File

@ -602,6 +602,8 @@ VCLRRB 000100 ..... ..... ..... 00111001101 @VX
# VSX Load/Store Instructions
LXSD 111001 ..... ..... .............. 10 @DS
STXSD 111101 ..... ..... .............. 10 @DS
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP

10
target/ppc/insn64.decode
View File

@ -32,6 +32,10 @@
...... ..... ra:5 ................ \
&PLS_D si=%pls_si rt=%rt_tsxp
@8LS_D ...... .. . .. r:1 .. .................. \
...... rt:5 ra:5 ................ \
&PLS_D si=%pls_si
# Format 8RR:D
%8rr_si 32:s16 0:16
%8rr_xt 16:1 21:5
@ -180,6 +184,12 @@ PSTFD 000001 10 0--.-- .................. \
### VSX instructions
PLXSD 000001 00 0--.-- .................. \
101010 ..... ..... ................ @8LS_D
PSTXSD 000001 00 0--.-- .................. \
101110 ..... ..... ................ @8LS_D
PLXV 000001 00 0--.-- .................. \
11001 ...... ..... ................ @8LS_D_TSX
PSTXV 000001 00 0--.-- .................. \

14
target/ppc/translate.c
View File

@ -6668,7 +6668,7 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
#include "translate/branch-impl.c.inc"
/* Handles lfdp, lxsd, lxssp */
/* Handles lfdp, lxssp */
static void gen_dform39(DisasContext *ctx)
{
switch (ctx->opcode & 0x3) {
@ -6677,11 +6677,6 @@ static void gen_dform39(DisasContext *ctx)
return gen_lfdp(ctx);
}
break;
case 2: /* lxsd */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_lxsd(ctx);
}
break;
case 3: /* lxssp */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_lxssp(ctx);
@ -6691,7 +6686,7 @@ static void gen_dform39(DisasContext *ctx)
return gen_invalid(ctx);
}
/* handles stfdp, lxv, stxsd, stxssp lxvx */
/* handles stfdp, lxv, stxssp lxvx */
static void gen_dform3D(DisasContext *ctx)
{
if ((ctx->opcode & 3) != 1) { /* DS-FORM */
@ -6701,11 +6696,6 @@ static void gen_dform3D(DisasContext *ctx)
return gen_stfdp(ctx);
}
break;
case 2: /* stxsd */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_stxsd(ctx);
}
break;
case 3: /* stxssp */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_stxssp(ctx);

55
target/ppc/translate/vsx-impl.c.inc
View File

@ -309,7 +309,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xth); \
}
VSX_LOAD_SCALAR_DS(lxsd, ld64_i64)
VSX_LOAD_SCALAR_DS(lxssp, ld32fs)
#define VSX_STORE_SCALAR(name, operation) \
@ -482,7 +481,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xth); \
}
VSX_STORE_SCALAR_DS(stxsd, st64_i64)
VSX_STORE_SCALAR_DS(stxssp, st32fs)
static void gen_mfvsrwz(DisasContext *ctx)
@ -2298,6 +2296,57 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
}
static bool do_lstxsd(DisasContext *ctx, int rt, int ra, TCGv displ, bool store)
{
TCGv ea;
TCGv_i64 xt;
MemOp mop;
if (store) {
REQUIRE_VECTOR(ctx);
} else {
REQUIRE_VSX(ctx);
}
xt = tcg_temp_new_i64();
mop = DEF_MEMOP(MO_UQ);
gen_set_access_type(ctx, ACCESS_INT);
ea = do_ea_calc(ctx, ra, displ);
if (store) {
get_cpu_vsr(xt, rt + 32, true);
tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
} else {
tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
set_cpu_vsr(rt + 32, xt, true);
set_cpu_vsr(rt + 32, tcg_constant_i64(0), false);
}
tcg_temp_free(ea);
tcg_temp_free_i64(xt);
return true;
}
static bool do_lstxsd_DS(DisasContext *ctx, arg_D *a, bool store)
{
return do_lstxsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), store);
}
static bool do_plstxsd_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
{
arg_D d;
if (!resolve_PLS_D(ctx, &d, a)) {
return true;
}
return do_lstxsd(ctx, d.rt, d.ra, tcg_constant_tl(d.si), store);
}
TRANS_FLAGS2(ISA300, LXSD, do_lstxsd_DS, false)
TRANS_FLAGS2(ISA300, STXSD, do_lstxsd_DS, true)
TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false)
TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false)
TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true)
@ -2306,6 +2355,8 @@ TRANS_FLAGS2(ISA300, STXVX, do_lstxv_X, true, false)
TRANS_FLAGS2(ISA300, LXVX, do_lstxv_X, false, false)
TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true)
TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true)
TRANS64_FLAGS2(ISA310, PLXSD, do_plstxsd_PLS_D, false)
TRANS64_FLAGS2(ISA310, PSTXSD, do_plstxsd_PLS_D, true)
TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false)
TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)