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tests/tcg/xtensa: update test_fp1 for DFPU

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DFPU sets Invalid flag in FSR when at least one argument of FP
comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole.
Add checks for FSR and expected FSR values.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2020-07-04 14:07:25 -07:00
parent 5c10f488ea
commit 7f4faa2185
1 changed files with 34 additions and 28 deletions
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62
tests/tcg/xtensa/test_fp1.S
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@ -1,4 +1,5 @@
#include "macros.inc"
#include "fpu.h"
test_suite fp1
@ -9,7 +10,7 @@ test_suite fp1
wfr \fr, a2
.endm
.macro test_ord_ex op, br, fr0, fr1, v0, v1, r
.macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
@ -20,65 +21,70 @@ test_suite fp1
movt a2, a3, \br
assert eqi, a2, \r
rur a2, fsr
#if DFPU
movi a3, \sr
assert eq, a2, a3
#else
assert eqi, a2, 0
#endif
.endm
.macro test_ord op, br, fr0, fr1, v0, v1, r
.macro test_ord op, br, fr0, fr1, v0, v1, r, sr
movi a2, 0
wur a2, fcr
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
movi a2, 0x7c
wur a2, fcr
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
.endm
.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI
test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa
test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab
test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba
test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI
test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa
test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN
test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN
test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN
test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN
test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na
test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na
test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na
test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na
test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II
test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN
test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI
.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI, qnan_sr
test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa, FSR__ /* ord == ord */
test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab, FSR__ /* ord < ord */
test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba, FSR__ /* ord > ord */
test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI, FSR__ /* ord +INF */
test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa, FSR__ /* +INF ord */
test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN, \qnan_sr /* ord -QNaN */
test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN, FSR_V /* ord -SNaN */
test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN, FSR_V /* ord +SNaN */
test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN, \qnan_sr /* ord +QNaN */
test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na, \qnan_sr /* -QNaN ord */
test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na, FSR_V /* -SNaN ord */
test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na, FSR_V /* +SNaN ord */
test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na, \qnan_sr /* +QNaN ord */
test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II, FSR__ /* +INF +INF */
test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN, \qnan_sr /* +INF +QNaN */
test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI, \qnan_sr /* +QNaN +INF */
.endm
test un_s
movi a2, 1
wsr a2, cpenable
test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1
test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, FSR__
test_end
test oeq_s
test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0
test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, FSR__
test_end
test ueq_s
test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1
test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, FSR__
test_end
test olt_s
test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0
test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, FSR_V
test_end
test ult_s
test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1
test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, FSR__
test_end
test ole_s
test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0
test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, FSR_V
test_end
test ule_s
test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1
test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, FSR__
test_end
.macro test_cond op, fr0, fr1, cr, v0, v1, r