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mos6522: only clear the shift register interrupt upon write

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According to the 6522 datasheet the shift register (SR) interrupt flag is
cleared upon write with no mention of any other interrupt flags.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Mark Cave-Ayland 2018-06-13 09:30:13 +01:00 committed by David Gibson
parent 52b438815e
commit 7f5d6517e3
1 changed files with 1 additions and 1 deletions
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2
hw/misc/mos6522.c
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@ -241,7 +241,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
break;
case VIA_REG_SR:
val = s->sr;
s->ifr &= ~(SR_INT | CB1_INT | CB2_INT);
s->ifr &= ~SR_INT;
mos6522_update_irq(s);
break;
case VIA_REG_ACR: