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target/arm: Create ARMVQMap

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Pull the three sve_vq_* values into a structure.
This will be reused for SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-06-20 10:51:56 -07:00 committed by Peter Maydell
parent 531cc51037
commit 7f9e25a6e4
4 changed files with 27 additions and 28 deletions
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29
target/arm/cpu.h
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@ -807,6 +807,19 @@ typedef enum ARMPSCIState {
typedef struct ARMISARegisters ARMISARegisters;
/*
* In map, each set bit is a supported vector length of (bit-number + 1) * 16
* bytes, i.e. each bit number + 1 is the vector length in quadwords.
*
* While processing properties during initialization, corresponding init bits
* are set for bits in sve_vq_map that have been set by properties.
*
* Bits set in supported represent valid vector lengths for the CPU type.
*/
typedef struct {
uint32_t map, init, supported;
} ARMVQMap;
/**
* ARMCPU:
* @env: #CPUARMState
@ -1055,21 +1068,7 @@ struct ArchCPU {
uint32_t sve_default_vq;
#endif
/*
* In sve_vq_map each set bit is a supported vector length of
* (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
* length in quadwords.
*
* While processing properties during initialization, corresponding
* sve_vq_init bits are set for bits in sve_vq_map that have been
* set by properties.
*
* Bits set in sve_vq_supported represent valid vector lengths for
* the CPU type.
*/
uint32_t sve_vq_map;
uint32_t sve_vq_init;
uint32_t sve_vq_supported;
ARMVQMap sve_vq;
/* Generic timer counter frequency, in Hz */
uint64_t gt_cntfrq_hz;

22
target/arm/cpu64.c
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@ -355,8 +355,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
* any of the above. Finally, if SVE is not disabled, then at least one
* vector length must be enabled.
*/
uint32_t vq_map = cpu->sve_vq_map;
uint32_t vq_init = cpu->sve_vq_init;
uint32_t vq_map = cpu->sve_vq.map;
uint32_t vq_init = cpu->sve_vq.init;
uint32_t vq_supported;
uint32_t vq_mask = 0;
uint32_t tmp, vq, max_vq = 0;
@ -369,14 +369,14 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
*/
if (kvm_enabled()) {
if (kvm_arm_sve_supported()) {
cpu->sve_vq_supported = kvm_arm_sve_get_vls(CPU(cpu));
vq_supported = cpu->sve_vq_supported;
cpu->sve_vq.supported = kvm_arm_sve_get_vls(CPU(cpu));
vq_supported = cpu->sve_vq.supported;
} else {
assert(!cpu_isar_feature(aa64_sve, cpu));
vq_supported = 0;
}
} else {
vq_supported = cpu->sve_vq_supported;
vq_supported = cpu->sve_vq.supported;
}
/*
@ -534,7 +534,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
/* From now on sve_max_vq is the actual maximum supported length. */
cpu->sve_max_vq = max_vq;
cpu->sve_vq_map = vq_map;
cpu->sve_vq.map = vq_map;
}
static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
@ -595,7 +595,7 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
if (!cpu_isar_feature(aa64_sve, cpu)) {
value = false;
} else {
value = extract32(cpu->sve_vq_map, vq - 1, 1);
value = extract32(cpu->sve_vq.map, vq - 1, 1);
}
visit_type_bool(v, name, &value, errp);
}
@ -611,8 +611,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
return;
}
cpu->sve_vq_map = deposit32(cpu->sve_vq_map, vq - 1, 1, value);
cpu->sve_vq_init |= 1 << (vq - 1);
cpu->sve_vq.map = deposit32(cpu->sve_vq.map, vq - 1, 1, value);
cpu->sve_vq.init |= 1 << (vq - 1);
}
static bool cpu_arm_get_sve(Object *obj, Error **errp)
@ -974,7 +974,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->dcz_blocksize = 7; /* 512 bytes */
#endif
cpu->sve_vq_supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
aarch64_add_pauth_properties(obj);
aarch64_add_sve_properties(obj);
@ -1023,7 +1023,7 @@ static void aarch64_a64fx_initfn(Object *obj)
/* The A64FX supports only 128, 256 and 512 bit vector lengths */
aarch64_add_sve_properties(obj);
cpu->sve_vq_supported = (1 << 0) /* 128bit */
cpu->sve_vq.supported = (1 << 0) /* 128bit */
| (1 << 1) /* 256bit */
| (1 << 3); /* 512bit */

2
target/arm/helper.c
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@ -6287,7 +6287,7 @@ uint32_t sve_vqm1_for_el(CPUARMState *env, int el)
len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
}
len = 31 - clz32(cpu->sve_vq_map & MAKE_64BIT_MASK(0, len + 1));
len = 31 - clz32(cpu->sve_vq.map & MAKE_64BIT_MASK(0, len + 1));
return len;
}

2
target/arm/kvm64.c
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@ -820,7 +820,7 @@ uint32_t kvm_arm_sve_get_vls(CPUState *cs)
static int kvm_arm_sve_set_vls(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq_map };
uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map };
struct kvm_one_reg reg = {
.id = KVM_REG_ARM64_SVE_VLS,
.addr = (uint64_t)&vls[0],