Merge branch 'arm-devs.next' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'arm-devs.next' of git://git.linaro.org/people/pmaydell/qemu-arm: xilinx_spips: QOM styling fixes xilinx_spips: Add missing dual-bus snoop commands xilinx_spips: Fix bus setup conditional check xilinx_spips: Set unused IRQs to NULL xilinx_zynq: added pl330 to machine model pl330: Initial version iov: Factor out hexdumper hw/vexpress: Set reset values for daughterboard oscillators hw/arm_sysctl: Implement SYS_CFG_OSC function hw/vexpress: Pass voltage sensor properties to sysctl device hw/arm_sysctl: Implement SYS_CFG_VOLT qdev: Implement (variable length) array properties hw/arm_sysctl: Convert from qdev init to instance_init hw/arm_sysctl: Implement SYS_CFG_DVIMODE as a no-op hw/arm_sysctl: Implement SYS_CFG_MUXFPGA writes as a no-op hw/arm_sysctl: Handle SYS_CFGCTRL in a more structured way hw/vexpress: Pass proc_id via VEDBoardInfo
This commit is contained in:
Blue Swirl
commit
7fb7377594
@ -42,6 +42,7 @@ CONFIG_PL110=y
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CONFIG_PL181=y
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CONFIG_PL190=y
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CONFIG_PL310=y
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CONFIG_PL330=y
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CONFIG_CADENCE=y
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CONFIG_XGMAC=y
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@ -98,6 +98,7 @@ common-obj-$(CONFIG_PL110) += pl110.o
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common-obj-$(CONFIG_PL181) += pl181.o
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common-obj-$(CONFIG_PL190) += pl190.o
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common-obj-$(CONFIG_PL310) += arm_l2x0.o
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common-obj-$(CONFIG_PL330) += pl330.o
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common-obj-$(CONFIG_VERSATILE_PCI) += versatile_pci.o
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common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
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common-obj-$(CONFIG_CADENCE) += cadence_uart.o
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@ -147,19 +147,24 @@ typedef struct VEDBoardInfo VEDBoardInfo;
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typedef void DBoardInitFn(const VEDBoardInfo *daughterboard,
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ram_addr_t ram_size,
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const char *cpu_model,
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qemu_irq *pic, uint32_t *proc_id);
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qemu_irq *pic);
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struct VEDBoardInfo {
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const hwaddr *motherboard_map;
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hwaddr loader_start;
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const hwaddr gic_cpu_if_addr;
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uint32_t proc_id;
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uint32_t num_voltage_sensors;
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const uint32_t *voltages;
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uint32_t num_clocks;
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const uint32_t *clocks;
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DBoardInitFn *init;
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};
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static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
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ram_addr_t ram_size,
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const char *cpu_model,
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qemu_irq *pic, uint32_t *proc_id)
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qemu_irq *pic)
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{
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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@ -175,8 +180,6 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
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cpu_model = "cortex-a9";
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}
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*proc_id = 0x0c000191;
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for (n = 0; n < smp_cpus; n++) {
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ARMCPU *cpu = cpu_arm_init(cpu_model);
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if (!cpu) {
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@ -247,17 +250,41 @@ static void a9_daughterboard_init(const VEDBoardInfo *daughterboard,
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sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
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}
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/* Voltage values for SYS_CFG_VOLT daughterboard registers;
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* values are in microvolts.
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*/
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static const uint32_t a9_voltages[] = {
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1000000, /* VD10 : 1.0V : SoC internal logic voltage */
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1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */
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1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */
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1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */
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900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */
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3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */
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};
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/* Reset values for daughterboard oscillators (in Hz) */
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static const uint32_t a9_clocks[] = {
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45000000, /* AMBA AXI ACLK: 45MHz */
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23750000, /* daughterboard CLCD clock: 23.75MHz */
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66670000, /* Test chip reference clock: 66.67MHz */
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};
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static const VEDBoardInfo a9_daughterboard = {
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.motherboard_map = motherboard_legacy_map,
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.loader_start = 0x60000000,
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.gic_cpu_if_addr = 0x1e000100,
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.proc_id = 0x0c000191,
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.num_voltage_sensors = ARRAY_SIZE(a9_voltages),
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.voltages = a9_voltages,
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.num_clocks = ARRAY_SIZE(a9_clocks),
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.clocks = a9_clocks,
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.init = a9_daughterboard_init,
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};
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static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
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ram_addr_t ram_size,
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const char *cpu_model,
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qemu_irq *pic, uint32_t *proc_id)
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qemu_irq *pic)
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{
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int n;
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MemoryRegion *sysmem = get_system_memory();
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@ -271,8 +298,6 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
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cpu_model = "cortex-a15";
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}
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*proc_id = 0x14000237;
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for (n = 0; n < smp_cpus; n++) {
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ARMCPU *cpu;
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qemu_irq *irqp;
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@ -340,10 +365,31 @@ static void a15_daughterboard_init(const VEDBoardInfo *daughterboard,
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/* 0x7ffd0000: PL354 static memory controller: not modelled */
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}
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static const uint32_t a15_voltages[] = {
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900000, /* Vcore: 0.9V : CPU core voltage */
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};
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static const uint32_t a15_clocks[] = {
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60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */
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0, /* OSCCLK1: reserved */
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0, /* OSCCLK2: reserved */
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0, /* OSCCLK3: reserved */
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40000000, /* OSCCLK4: 40MHz : external AXI master clock */
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23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */
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50000000, /* OSCCLK6: 50MHz : static memory controller clock */
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60000000, /* OSCCLK7: 60MHz : SYSCLK reference */
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40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */
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};
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static const VEDBoardInfo a15_daughterboard = {
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.motherboard_map = motherboard_aseries_map,
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.loader_start = 0x80000000,
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.gic_cpu_if_addr = 0x2c002000,
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.proc_id = 0x14000237,
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.num_voltage_sensors = ARRAY_SIZE(a15_voltages),
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.voltages = a15_voltages,
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.num_clocks = ARRAY_SIZE(a15_clocks),
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.clocks = a15_clocks,
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.init = a15_daughterboard_init,
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};
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@ -352,7 +398,6 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
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{
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DeviceState *dev, *sysctl, *pl041;
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qemu_irq pic[64];
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uint32_t proc_id;
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uint32_t sys_id;
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DriveInfo *dinfo;
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ram_addr_t vram_size, sram_size;
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@ -360,9 +405,9 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
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MemoryRegion *vram = g_new(MemoryRegion, 1);
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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const hwaddr *map = daughterboard->motherboard_map;
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int i;
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daughterboard->init(daughterboard, args->ram_size, args->cpu_model,
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pic, &proc_id);
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daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic);
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/* Motherboard peripherals: the wiring is the same but the
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* addresses vary between the legacy and A-Series memory maps.
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@ -372,7 +417,21 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
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sysctl = qdev_create(NULL, "realview_sysctl");
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qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
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qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
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qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
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qdev_prop_set_uint32(sysctl, "len-db-voltage",
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daughterboard->num_voltage_sensors);
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for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
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char *propname = g_strdup_printf("db-voltage[%d]", i);
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qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
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g_free(propname);
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}
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qdev_prop_set_uint32(sysctl, "len-db-clock",
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daughterboard->num_clocks);
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for (i = 0; i < daughterboard->num_clocks; i++) {
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char *propname = g_strdup_printf("db-clock[%d]", i);
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qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
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g_free(propname);
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}
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qdev_init_nofail(sysctl);
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sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
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@ -35,6 +35,10 @@
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#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
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static const int dma_irqs[8] = {
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46, 47, 48, 49, 72, 73, 74, 75
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};
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static struct arm_boot_info zynq_binfo = {};
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static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
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@ -196,6 +200,26 @@ static void zynq_init(QEMUMachineInitArgs *args)
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
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dev = qdev_create(NULL, "pl330");
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qdev_prop_set_uint8(dev, "num_chnls", 8);
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qdev_prop_set_uint8(dev, "num_periph_req", 4);
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qdev_prop_set_uint8(dev, "num_events", 16);
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qdev_prop_set_uint8(dev, "data_width", 64);
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qdev_prop_set_uint8(dev, "wr_cap", 8);
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qdev_prop_set_uint8(dev, "wr_q_dep", 16);
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qdev_prop_set_uint8(dev, "rd_cap", 8);
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qdev_prop_set_uint8(dev, "rd_q_dep", 16);
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qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, 0xF8003000);
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sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
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for (n = 0; n < 8; ++n) { /* event irqs */
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sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
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}
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zynq_binfo.ram_size = ram_size;
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zynq_binfo.kernel_filename = kernel_filename;
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zynq_binfo.kernel_cmdline = kernel_cmdline;
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261
hw/arm_sysctl.c
261
hw/arm_sysctl.c
@ -9,6 +9,7 @@
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#include "hw/hw.h"
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#include "qemu/timer.h"
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#include "qemu/bitops.h"
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#include "hw/sysbus.h"
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#include "hw/primecell.h"
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#include "sysemu/sysemu.h"
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@ -34,11 +35,17 @@ typedef struct {
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uint32_t sys_cfgctrl;
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uint32_t sys_cfgstat;
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uint32_t sys_clcd;
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uint32_t mb_clock[6];
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uint32_t *db_clock;
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uint32_t db_num_vsensors;
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uint32_t *db_voltage;
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uint32_t db_num_clocks;
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uint32_t *db_clock_reset;
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} arm_sysctl_state;
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static const VMStateDescription vmstate_arm_sysctl = {
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.name = "realview_sysctl",
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.version_id = 3,
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.version_id = 4,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(leds, arm_sysctl_state),
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@ -53,6 +60,9 @@ static const VMStateDescription vmstate_arm_sysctl = {
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VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
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VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
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VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
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VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks,
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4, vmstate_info_uint32, uint32_t),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -76,6 +86,7 @@ static int board_id(arm_sysctl_state *s)
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static void arm_sysctl_reset(DeviceState *d)
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{
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arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
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int i;
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s->leds = 0;
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s->lockval = 0;
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@ -83,6 +94,17 @@ static void arm_sysctl_reset(DeviceState *d)
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s->cfgdata2 = 0;
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s->flags = 0;
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s->resetlevel = 0;
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/* Motherboard oscillators (in Hz) */
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s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */
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s->mb_clock[1] = 23750000; /* motherboard CLCD clock: 23.75MHz */
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s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */
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s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */
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s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */
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s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */
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/* Daughterboard oscillators: reset from property values */
|
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for (i = 0; i < s->db_num_clocks; i++) {
|
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s->db_clock[i] = s->db_clock_reset[i];
|
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}
|
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if (board_id(s) == BOARD_ID_VEXPRESS) {
|
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/* On VExpress this register will RAZ/WI */
|
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s->sys_clcd = 0;
|
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@ -191,6 +213,166 @@ static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
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}
|
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}
|
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|
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/* SYS_CFGCTRL functions */
|
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#define SYS_CFG_OSC 1
|
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#define SYS_CFG_VOLT 2
|
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#define SYS_CFG_AMP 3
|
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#define SYS_CFG_TEMP 4
|
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#define SYS_CFG_RESET 5
|
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#define SYS_CFG_SCC 6
|
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#define SYS_CFG_MUXFPGA 7
|
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#define SYS_CFG_SHUTDOWN 8
|
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#define SYS_CFG_REBOOT 9
|
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#define SYS_CFG_DVIMODE 11
|
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#define SYS_CFG_POWER 12
|
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#define SYS_CFG_ENERGY 13
|
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|
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/* SYS_CFGCTRL site field values */
|
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#define SYS_CFG_SITE_MB 0
|
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#define SYS_CFG_SITE_DB1 1
|
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#define SYS_CFG_SITE_DB2 2
|
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|
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/**
|
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* vexpress_cfgctrl_read:
|
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* @s: arm_sysctl_state pointer
|
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* @dcc, @function, @site, @position, @device: split out values from
|
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* SYS_CFGCTRL register
|
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* @val: pointer to where to put the read data on success
|
||||
*
|
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* Handle a VExpress SYS_CFGCTRL register read. On success, return true and
|
||||
* write the read value to *val. On failure, return false (and val may
|
||||
* or may not be written to).
|
||||
*/
|
||||
static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc,
|
||||
unsigned int function, unsigned int site,
|
||||
unsigned int position, unsigned int device,
|
||||
uint32_t *val)
|
||||
{
|
||||
/* We don't support anything other than DCC 0, board stack position 0
|
||||
* or sites other than motherboard/daughterboard:
|
||||
*/
|
||||
if (dcc != 0 || position != 0 ||
|
||||
(site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
|
||||
goto cfgctrl_unimp;
|
||||
}
|
||||
|
||||
switch (function) {
|
||||
case SYS_CFG_VOLT:
|
||||
if (site == SYS_CFG_SITE_DB1 && device < s->db_num_vsensors) {
|
||||
*val = s->db_voltage[device];
|
||||
return true;
|
||||
}
|
||||
if (site == SYS_CFG_SITE_MB && device == 0) {
|
||||
/* There is only one motherboard voltage sensor:
|
||||
* VIO : 3.3V : bus voltage between mother and daughterboard
|
||||
*/
|
||||
*val = 3300000;
|
||||
return true;
|
||||
}
|
||||
break;
|
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case SYS_CFG_OSC:
|
||||
if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) {
|
||||
/* motherboard clock */
|
||||
*val = s->mb_clock[device];
|
||||
return true;
|
||||
}
|
||||
if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
|
||||
/* daughterboard clock */
|
||||
*val = s->db_clock[device];
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
cfgctrl_unimp:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"arm_sysctl: Unimplemented SYS_CFGCTRL read of function "
|
||||
"0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
|
||||
function, dcc, site, position, device);
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* vexpress_cfgctrl_write:
|
||||
* @s: arm_sysctl_state pointer
|
||||
* @dcc, @function, @site, @position, @device: split out values from
|
||||
* SYS_CFGCTRL register
|
||||
* @val: data to write
|
||||
*
|
||||
* Handle a VExpress SYS_CFGCTRL register write. On success, return true.
|
||||
* On failure, return false.
|
||||
*/
|
||||
static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
|
||||
unsigned int function, unsigned int site,
|
||||
unsigned int position, unsigned int device,
|
||||
uint32_t val)
|
||||
{
|
||||
/* We don't support anything other than DCC 0, board stack position 0
|
||||
* or sites other than motherboard/daughterboard:
|
||||
*/
|
||||
if (dcc != 0 || position != 0 ||
|
||||
(site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
|
||||
goto cfgctrl_unimp;
|
||||
}
|
||||
|
||||
switch (function) {
|
||||
case SYS_CFG_OSC:
|
||||
if (site == SYS_CFG_SITE_MB && device < sizeof(s->mb_clock)) {
|
||||
/* motherboard clock */
|
||||
s->mb_clock[device] = val;
|
||||
return true;
|
||||
}
|
||||
if (site == SYS_CFG_SITE_DB1 && device < s->db_num_clocks) {
|
||||
/* daughterboard clock */
|
||||
s->db_clock[device] = val;
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
case SYS_CFG_MUXFPGA:
|
||||
if (site == SYS_CFG_SITE_MB && device == 0) {
|
||||
/* Select whether video output comes from motherboard
|
||||
* or daughterboard: log and ignore as QEMU doesn't
|
||||
* support this.
|
||||
*/
|
||||
qemu_log_mask(LOG_UNIMP, "arm_sysctl: selection of video output "
|
||||
"not supported, ignoring\n");
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
case SYS_CFG_SHUTDOWN:
|
||||
if (site == SYS_CFG_SITE_MB && device == 0) {
|
||||
qemu_system_shutdown_request();
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
case SYS_CFG_REBOOT:
|
||||
if (site == SYS_CFG_SITE_MB && device == 0) {
|
||||
qemu_system_reset_request();
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
case SYS_CFG_DVIMODE:
|
||||
if (site == SYS_CFG_SITE_MB && device == 0) {
|
||||
/* Selecting DVI mode is meaningless for QEMU: we will
|
||||
* always display the output correctly according to the
|
||||
* pixel height/width programmed into the CLCD controller.
|
||||
*/
|
||||
return true;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
cfgctrl_unimp:
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
|
||||
"0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
|
||||
function, dcc, site, position, device);
|
||||
return false;
|
||||
}
|
||||
|
||||
static void arm_sysctl_write(void *opaque, hwaddr offset,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
@ -322,17 +504,33 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
|
||||
if (board_id(s) != BOARD_ID_VEXPRESS) {
|
||||
goto bad_reg;
|
||||
}
|
||||
s->sys_cfgctrl = val & ~(3 << 18);
|
||||
s->sys_cfgstat = 1; /* complete */
|
||||
switch (s->sys_cfgctrl) {
|
||||
case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */
|
||||
qemu_system_shutdown_request();
|
||||
break;
|
||||
case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */
|
||||
qemu_system_reset_request();
|
||||
break;
|
||||
default:
|
||||
s->sys_cfgstat |= 2; /* error */
|
||||
/* Undefined bits [19:18] are RAZ/WI, and writing to
|
||||
* the start bit just triggers the action; it always reads
|
||||
* as zero.
|
||||
*/
|
||||
s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
|
||||
if (val & (1 << 31)) {
|
||||
/* Start bit set -- actually do something */
|
||||
unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
|
||||
unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
|
||||
unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
|
||||
unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
|
||||
unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
|
||||
s->sys_cfgstat = 1; /* complete */
|
||||
if (s->sys_cfgctrl & (1 << 30)) {
|
||||
if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
|
||||
device, s->sys_cfgdata)) {
|
||||
s->sys_cfgstat |= 2; /* error */
|
||||
}
|
||||
} else {
|
||||
uint32_t val;
|
||||
if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
|
||||
device, &val)) {
|
||||
s->sys_cfgstat |= 2; /* error */
|
||||
} else {
|
||||
s->sys_cfgdata = val;
|
||||
}
|
||||
}
|
||||
}
|
||||
s->sys_cfgctrl &= ~(1 << 31);
|
||||
return;
|
||||
@ -385,29 +583,50 @@ static void arm_sysctl_gpio_set(void *opaque, int line, int level)
|
||||
}
|
||||
}
|
||||
|
||||
static int arm_sysctl_init(SysBusDevice *dev)
|
||||
static void arm_sysctl_init(Object *obj)
|
||||
{
|
||||
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
|
||||
DeviceState *dev = DEVICE(obj);
|
||||
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
|
||||
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sd);
|
||||
|
||||
memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
|
||||
qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
|
||||
return 0;
|
||||
sysbus_init_mmio(sd, &s->iomem);
|
||||
qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2);
|
||||
qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1);
|
||||
}
|
||||
|
||||
static void arm_sysctl_realize(DeviceState *d, Error **errp)
|
||||
{
|
||||
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
|
||||
s->db_clock = g_new0(uint32_t, s->db_num_clocks);
|
||||
}
|
||||
|
||||
static void arm_sysctl_finalize(Object *obj)
|
||||
{
|
||||
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
||||
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
|
||||
g_free(s->db_voltage);
|
||||
g_free(s->db_clock);
|
||||
g_free(s->db_clock_reset);
|
||||
}
|
||||
|
||||
static Property arm_sysctl_properties[] = {
|
||||
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
|
||||
DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
|
||||
/* Daughterboard power supply voltages (as reported via SYS_CFG) */
|
||||
DEFINE_PROP_ARRAY("db-voltage", arm_sysctl_state, db_num_vsensors,
|
||||
db_voltage, qdev_prop_uint32, uint32_t),
|
||||
/* Daughterboard clock reset values (as reported via SYS_CFG) */
|
||||
DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks,
|
||||
db_clock_reset, qdev_prop_uint32, uint32_t),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void arm_sysctl_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||||
|
||||
k->init = arm_sysctl_init;
|
||||
dc->realize = arm_sysctl_realize;
|
||||
dc->reset = arm_sysctl_reset;
|
||||
dc->vmsd = &vmstate_arm_sysctl;
|
||||
dc->props = arm_sysctl_properties;
|
||||
@ -417,6 +636,8 @@ static const TypeInfo arm_sysctl_info = {
|
||||
.name = "realview_sysctl",
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(arm_sysctl_state),
|
||||
.instance_init = arm_sysctl_init,
|
||||
.instance_finalize = arm_sysctl_finalize,
|
||||
.class_init = arm_sysctl_class_init,
|
||||
};
|
||||
|
||||
|
||||
1654
hw/pl330.c
Normal file
1654
hw/pl330.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -175,6 +175,9 @@ struct Property {
|
||||
uint8_t bitnr;
|
||||
uint8_t qtype;
|
||||
int64_t defval;
|
||||
int arrayoffset;
|
||||
PropertyInfo *arrayinfo;
|
||||
int arrayfieldsize;
|
||||
};
|
||||
|
||||
struct PropertyInfo {
|
||||
|
||||
@ -779,6 +779,110 @@ PropertyInfo qdev_prop_pci_host_devaddr = {
|
||||
.set = set_pci_host_devaddr,
|
||||
};
|
||||
|
||||
/* --- support for array properties --- */
|
||||
|
||||
/* Used as an opaque for the object properties we add for each
|
||||
* array element. Note that the struct Property must be first
|
||||
* in the struct so that a pointer to this works as the opaque
|
||||
* for the underlying element's property hooks as well as for
|
||||
* our own release callback.
|
||||
*/
|
||||
typedef struct {
|
||||
struct Property prop;
|
||||
char *propname;
|
||||
ObjectPropertyRelease *release;
|
||||
} ArrayElementProperty;
|
||||
|
||||
/* object property release callback for array element properties:
|
||||
* we call the underlying element's property release hook, and
|
||||
* then free the memory we allocated when we added the property.
|
||||
*/
|
||||
static void array_element_release(Object *obj, const char *name, void *opaque)
|
||||
{
|
||||
ArrayElementProperty *p = opaque;
|
||||
if (p->release) {
|
||||
p->release(obj, name, opaque);
|
||||
}
|
||||
g_free(p->propname);
|
||||
g_free(p);
|
||||
}
|
||||
|
||||
static void set_prop_arraylen(Object *obj, Visitor *v, void *opaque,
|
||||
const char *name, Error **errp)
|
||||
{
|
||||
/* Setter for the property which defines the length of a
|
||||
* variable-sized property array. As well as actually setting the
|
||||
* array-length field in the device struct, we have to create the
|
||||
* array itself and dynamically add the corresponding properties.
|
||||
*/
|
||||
DeviceState *dev = DEVICE(obj);
|
||||
Property *prop = opaque;
|
||||
uint32_t *alenptr = qdev_get_prop_ptr(dev, prop);
|
||||
void **arrayptr = (void *)dev + prop->arrayoffset;
|
||||
void *eltptr;
|
||||
const char *arrayname;
|
||||
int i;
|
||||
|
||||
if (dev->realized) {
|
||||
error_set(errp, QERR_PERMISSION_DENIED);
|
||||
return;
|
||||
}
|
||||
if (*alenptr) {
|
||||
error_setg(errp, "array size property %s may not be set more than once",
|
||||
name);
|
||||
return;
|
||||
}
|
||||
visit_type_uint32(v, alenptr, name, errp);
|
||||
if (error_is_set(errp)) {
|
||||
return;
|
||||
}
|
||||
if (!*alenptr) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* DEFINE_PROP_ARRAY guarantees that name should start with this prefix;
|
||||
* strip it off so we can get the name of the array itself.
|
||||
*/
|
||||
assert(strncmp(name, PROP_ARRAY_LEN_PREFIX,
|
||||
strlen(PROP_ARRAY_LEN_PREFIX)) == 0);
|
||||
arrayname = name + strlen(PROP_ARRAY_LEN_PREFIX);
|
||||
|
||||
/* Note that it is the responsibility of the individual device's deinit
|
||||
* to free the array proper.
|
||||
*/
|
||||
*arrayptr = eltptr = g_malloc0(*alenptr * prop->arrayfieldsize);
|
||||
for (i = 0; i < *alenptr; i++, eltptr += prop->arrayfieldsize) {
|
||||
char *propname = g_strdup_printf("%s[%d]", arrayname, i);
|
||||
ArrayElementProperty *arrayprop = g_new0(ArrayElementProperty, 1);
|
||||
arrayprop->release = prop->arrayinfo->release;
|
||||
arrayprop->propname = propname;
|
||||
arrayprop->prop.info = prop->arrayinfo;
|
||||
arrayprop->prop.name = propname;
|
||||
/* This ugly piece of pointer arithmetic sets up the offset so
|
||||
* that when the underlying get/set hooks call qdev_get_prop_ptr
|
||||
* they get the right answer despite the array element not actually
|
||||
* being inside the device struct.
|
||||
*/
|
||||
arrayprop->prop.offset = eltptr - (void *)dev;
|
||||
assert(qdev_get_prop_ptr(dev, &arrayprop->prop) == eltptr);
|
||||
object_property_add(obj, propname,
|
||||
arrayprop->prop.info->name,
|
||||
arrayprop->prop.info->get,
|
||||
arrayprop->prop.info->set,
|
||||
array_element_release,
|
||||
arrayprop, errp);
|
||||
if (error_is_set(errp)) {
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
PropertyInfo qdev_prop_arraylen = {
|
||||
.name = "uint32",
|
||||
.get = get_uint32,
|
||||
.set = set_prop_arraylen,
|
||||
};
|
||||
|
||||
/* --- public helpers --- */
|
||||
|
||||
static Property *qdev_prop_walk(Property *props, const char *name)
|
||||
|
||||
@ -26,6 +26,7 @@ extern PropertyInfo qdev_prop_vlan;
|
||||
extern PropertyInfo qdev_prop_pci_devfn;
|
||||
extern PropertyInfo qdev_prop_blocksize;
|
||||
extern PropertyInfo qdev_prop_pci_host_devaddr;
|
||||
extern PropertyInfo qdev_prop_arraylen;
|
||||
|
||||
#define DEFINE_PROP(_name, _state, _field, _prop, _type) { \
|
||||
.name = (_name), \
|
||||
@ -51,6 +52,44 @@ extern PropertyInfo qdev_prop_pci_host_devaddr;
|
||||
.defval = (bool)_defval, \
|
||||
}
|
||||
|
||||
#define PROP_ARRAY_LEN_PREFIX "len-"
|
||||
|
||||
/**
|
||||
* DEFINE_PROP_ARRAY:
|
||||
* @_name: name of the array
|
||||
* @_state: name of the device state structure type
|
||||
* @_field: uint32_t field in @_state to hold the array length
|
||||
* @_arrayfield: field in @_state (of type '@_arraytype *') which
|
||||
* will point to the array
|
||||
* @_arrayprop: PropertyInfo defining what property the array elements have
|
||||
* @_arraytype: C type of the array elements
|
||||
*
|
||||
* Define device properties for a variable-length array _name. A
|
||||
* static property "len-arrayname" is defined. When the device creator
|
||||
* sets this property to the desired length of array, further dynamic
|
||||
* properties "arrayname[0]", "arrayname[1]", ... are defined so the
|
||||
* device creator can set the array element values. Setting the
|
||||
* "len-arrayname" property more than once is an error.
|
||||
*
|
||||
* When the array length is set, the @_field member of the device
|
||||
* struct is set to the array length, and @_arrayfield is set to point
|
||||
* to (zero-initialised) memory allocated for the array. For a zero
|
||||
* length array, @_field will be set to 0 and @_arrayfield to NULL.
|
||||
* It is the responsibility of the device deinit code to free the
|
||||
* @_arrayfield memory.
|
||||
*/
|
||||
#define DEFINE_PROP_ARRAY(_name, _state, _field, \
|
||||
_arrayfield, _arrayprop, _arraytype) { \
|
||||
.name = (PROP_ARRAY_LEN_PREFIX _name), \
|
||||
.info = &(qdev_prop_arraylen), \
|
||||
.offset = offsetof(_state, _field) \
|
||||
+ type_check(uint32_t, typeof_field(_state, _field)), \
|
||||
.qtype = QTYPE_QINT, \
|
||||
.arrayinfo = &(_arrayprop), \
|
||||
.arrayfieldsize = sizeof(_arraytype), \
|
||||
.arrayoffset = offsetof(_state, _arrayfield), \
|
||||
}
|
||||
|
||||
#define DEFINE_PROP_UINT8(_n, _s, _f, _d) \
|
||||
DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_uint8, uint8_t)
|
||||
#define DEFINE_PROP_UINT16(_n, _s, _f, _d) \
|
||||
|
||||
@ -115,6 +115,19 @@
|
||||
#define SNOOP_NONE 0xFE
|
||||
#define SNOOP_STRIPING 0
|
||||
|
||||
typedef enum {
|
||||
READ = 0x3,
|
||||
FAST_READ = 0xb,
|
||||
DOR = 0x3b,
|
||||
QOR = 0x6b,
|
||||
DIOR = 0xbb,
|
||||
QIOR = 0xeb,
|
||||
|
||||
PP = 0x2,
|
||||
DPP = 0xa2,
|
||||
QPP = 0x32,
|
||||
} FlashCMD;
|
||||
|
||||
typedef struct {
|
||||
SysBusDevice busdev;
|
||||
MemoryRegion iomem;
|
||||
@ -141,10 +154,15 @@ typedef struct {
|
||||
hwaddr lqspi_cached_addr;
|
||||
} XilinxSPIPS;
|
||||
|
||||
#define TYPE_XILINX_SPIPS "xilinx,spips"
|
||||
|
||||
#define XILINX_SPIPS(obj) \
|
||||
OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
|
||||
|
||||
static inline int num_effective_busses(XilinxSPIPS *s)
|
||||
{
|
||||
return (s->regs[R_LQSPI_STS] & LQSPI_CFG_SEP_BUS &&
|
||||
s->regs[R_LQSPI_STS] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
|
||||
return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
|
||||
s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
|
||||
}
|
||||
|
||||
static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
|
||||
@ -197,7 +215,7 @@ static void xilinx_spips_update_ixr(XilinxSPIPS *s)
|
||||
|
||||
static void xilinx_spips_reset(DeviceState *d)
|
||||
{
|
||||
XilinxSPIPS *s = DO_UPCAST(XilinxSPIPS, busdev.qdev, d);
|
||||
XilinxSPIPS *s = XILINX_SPIPS(d);
|
||||
|
||||
int i;
|
||||
for (i = 0; i < R_MAX; i++) {
|
||||
@ -251,15 +269,19 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
|
||||
switch (s->snoop_state) {
|
||||
case (SNOOP_CHECKING):
|
||||
switch (tx) { /* new instruction code */
|
||||
case 0x0b: /* dual/quad output read DOR/QOR */
|
||||
case 0x6b:
|
||||
case READ: /* 3 address bytes, no dummy bytes/cycles */
|
||||
case PP:
|
||||
case DPP:
|
||||
case QPP:
|
||||
s->snoop_state = 3;
|
||||
break;
|
||||
case FAST_READ: /* 3 address bytes, 1 dummy byte */
|
||||
case DOR:
|
||||
case QOR:
|
||||
case DIOR: /* FIXME: these vary between vendor - set to spansion */
|
||||
s->snoop_state = 4;
|
||||
break;
|
||||
/* FIXME: these vary between vendor - set to spansion */
|
||||
case 0xbb: /* high performance dual read DIOR */
|
||||
s->snoop_state = 4;
|
||||
break;
|
||||
case 0xeb: /* high performance quad read QIOR */
|
||||
case QIOR: /* 3 address bytes, 2 dummy bytes */
|
||||
s->snoop_state = 6;
|
||||
break;
|
||||
default:
|
||||
@ -483,9 +505,10 @@ static const MemoryRegionOps lqspi_ops = {
|
||||
}
|
||||
};
|
||||
|
||||
static int xilinx_spips_init(SysBusDevice *dev)
|
||||
static void xilinx_spips_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
XilinxSPIPS *s = FROM_SYSBUS(typeof(*s), dev);
|
||||
XilinxSPIPS *s = XILINX_SPIPS(dev);
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
||||
int i;
|
||||
|
||||
DB_PRINT("inited device model\n");
|
||||
@ -494,31 +517,29 @@ static int xilinx_spips_init(SysBusDevice *dev)
|
||||
for (i = 0; i < s->num_busses; ++i) {
|
||||
char bus_name[16];
|
||||
snprintf(bus_name, 16, "spi%d", i);
|
||||
s->spi[i] = ssi_create_bus(&dev->qdev, bus_name);
|
||||
s->spi[i] = ssi_create_bus(dev, bus_name);
|
||||
}
|
||||
|
||||
s->cs_lines = g_new(qemu_irq, s->num_cs * s->num_busses);
|
||||
s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
|
||||
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
|
||||
ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
|
||||
sysbus_init_irq(dev, &s->irq);
|
||||
sysbus_init_irq(sbd, &s->irq);
|
||||
for (i = 0; i < s->num_cs * s->num_busses; ++i) {
|
||||
sysbus_init_irq(dev, &s->cs_lines[i]);
|
||||
sysbus_init_irq(sbd, &s->cs_lines[i]);
|
||||
}
|
||||
|
||||
memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
sysbus_init_mmio(sbd, &s->iomem);
|
||||
|
||||
memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
|
||||
(1 << LQSPI_ADDRESS_BITS) * 2);
|
||||
sysbus_init_mmio(dev, &s->mmlqspi);
|
||||
sysbus_init_mmio(sbd, &s->mmlqspi);
|
||||
|
||||
s->irqline = -1;
|
||||
s->lqspi_cached_addr = ~0ULL;
|
||||
|
||||
fifo8_create(&s->rx_fifo, RXFF_A);
|
||||
fifo8_create(&s->tx_fifo, TXFF_A);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int xilinx_spips_post_load(void *opaque, int version_id)
|
||||
@ -552,16 +573,15 @@ static Property xilinx_spips_properties[] = {
|
||||
static void xilinx_spips_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
||||
|
||||
sdc->init = xilinx_spips_init;
|
||||
dc->realize = xilinx_spips_realize;
|
||||
dc->reset = xilinx_spips_reset;
|
||||
dc->props = xilinx_spips_properties;
|
||||
dc->vmsd = &vmstate_xilinx_spips;
|
||||
}
|
||||
|
||||
static const TypeInfo xilinx_spips_info = {
|
||||
.name = "xilinx,spips",
|
||||
.name = TYPE_XILINX_SPIPS,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(XilinxSPIPS),
|
||||
.class_init = xilinx_spips_class_init,
|
||||
|
||||
@ -442,4 +442,10 @@ int64_t pow2floor(int64_t value);
|
||||
int uleb128_encode_small(uint8_t *out, uint32_t n);
|
||||
int uleb128_decode_small(const uint8_t *in, uint32_t *n);
|
||||
|
||||
/*
|
||||
* Hexdump a buffer to a file. An optional string prefix is added to every line
|
||||
*/
|
||||
|
||||
void hexdump(const char *buf, FILE *fp, const char *prefix, size_t size);
|
||||
|
||||
#endif
|
||||
|
||||
@ -9,3 +9,4 @@ util-obj-y += error.o qemu-error.o
|
||||
util-obj-$(CONFIG_POSIX) += compatfd.o
|
||||
util-obj-y += iov.o aes.o qemu-config.o qemu-sockets.o uri.o notify.o
|
||||
util-obj-y += qemu-option.o qemu-progress.o
|
||||
util-obj-y += hexdump.o
|
||||
|
||||
37
util/hexdump.c
Normal file
37
util/hexdump.c
Normal file
@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Helper to hexdump a buffer
|
||||
*
|
||||
* Copyright (c) 2013 Red Hat, Inc.
|
||||
* Copyright (c) 2013 Gerd Hoffmann <kraxel@redhat.com>
|
||||
* Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
|
||||
* Copyright (c) 2013 Xilinx, Inc
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2. See
|
||||
* the COPYING file in the top-level directory.
|
||||
*
|
||||
* Contributions after 2012-01-13 are licensed under the terms of the
|
||||
* GNU GPL, version 2 or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include "qemu-common.h"
|
||||
|
||||
void hexdump(const char *buf, FILE *fp, const char *prefix, size_t size)
|
||||
{
|
||||
unsigned int b;
|
||||
|
||||
for (b = 0; b < size; b++) {
|
||||
if ((b % 16) == 0) {
|
||||
fprintf(fp, "%s: %04x:", prefix, b);
|
||||
}
|
||||
if ((b % 4) == 0) {
|
||||
fprintf(fp, " ");
|
||||
}
|
||||
fprintf(fp, " %02x", (unsigned char)buf[b]);
|
||||
if ((b % 16) == 15) {
|
||||
fprintf(fp, "\n");
|
||||
}
|
||||
}
|
||||
if ((b % 16) != 0) {
|
||||
fprintf(fp, "\n");
|
||||
}
|
||||
}
|
||||
34
util/iov.c
34
util/iov.c
@ -201,32 +201,18 @@ ssize_t iov_send_recv(int sockfd, struct iovec *iov, unsigned iov_cnt,
|
||||
void iov_hexdump(const struct iovec *iov, const unsigned int iov_cnt,
|
||||
FILE *fp, const char *prefix, size_t limit)
|
||||
{
|
||||
unsigned int i, v, b;
|
||||
uint8_t *c;
|
||||
int v;
|
||||
size_t size = 0;
|
||||
char *buf;
|
||||
|
||||
c = iov[0].iov_base;
|
||||
for (i = 0, v = 0, b = 0; b < limit; i++, b++) {
|
||||
if (i == iov[v].iov_len) {
|
||||
i = 0; v++;
|
||||
if (v == iov_cnt) {
|
||||
break;
|
||||
}
|
||||
c = iov[v].iov_base;
|
||||
}
|
||||
if ((b % 16) == 0) {
|
||||
fprintf(fp, "%s: %04x:", prefix, b);
|
||||
}
|
||||
if ((b % 4) == 0) {
|
||||
fprintf(fp, " ");
|
||||
}
|
||||
fprintf(fp, " %02x", c[i]);
|
||||
if ((b % 16) == 15) {
|
||||
fprintf(fp, "\n");
|
||||
}
|
||||
}
|
||||
if ((b % 16) != 0) {
|
||||
fprintf(fp, "\n");
|
||||
for (v = 0; v < iov_cnt; v++) {
|
||||
size += iov[v].iov_len;
|
||||
}
|
||||
size = size > limit ? limit : size;
|
||||
buf = g_malloc(size);
|
||||
iov_to_buf(iov, iov_cnt, 0, buf, size);
|
||||
hexdump(buf, fp, prefix, size);
|
||||
g_free(buf);
|
||||
}
|
||||
|
||||
unsigned iov_copy(struct iovec *dst_iov, unsigned int dst_iov_cnt,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user