target/ppc: Remove unused PPC 460 and 460F definitions
We don't have any 460 or 460F CPUs in QEMU, so the init functions are just dead code. Let's simply remove them (translate_init.c is already big enough without them). Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Thomas Huth
David Gibson
parent
a4f3885c74
commit
7ff26aa6c6
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@ -4176,223 +4176,6 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
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POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
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}
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static void init_proc_460 (CPUPPCState *env)
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{
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/* Time base */
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gen_tbl(env);
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gen_spr_BookE(env, 0x000000000000FFFFULL);
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gen_spr_440(env);
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gen_spr_usprgh(env);
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/* Processor identification */
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spr_register(env, SPR_BOOKE_PIR, "PIR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_pir,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_IAC3, "IAC3",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_IAC4, "IAC4",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_DVC1, "DVC1",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_DVC2, "DVC2",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_MCSR, "MCSR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_440_CCR1, "CCR1",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
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&spr_read_generic, &spr_write_generic,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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env->tlb_type = TLB_EMB;
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#endif
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init_excp_BookE(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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/* XXX: TODO: allocate internal IRQ controller */
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SET_FIT_PERIOD(12, 16, 20, 24);
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SET_WDT_PERIOD(20, 24, 28, 32);
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}
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POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
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dc->desc = "PowerPC 460 (guessed)";
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pcc->init_proc = init_proc_460;
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pcc->check_pow = check_pow_nocheck;
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pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
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PPC_DCR | PPC_DCRX | PPC_DCRUX |
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PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
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PPC_CACHE | PPC_CACHE_ICBI |
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PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
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PPC_MEM_TLBSYNC | PPC_TLBIVA |
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PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
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PPC_440_SPEC;
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pcc->msr_mask = (1ull << MSR_POW) |
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(1ull << MSR_CE) |
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(1ull << MSR_EE) |
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(1ull << MSR_PR) |
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(1ull << MSR_FP) |
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(1ull << MSR_ME) |
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(1ull << MSR_FE0) |
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(1ull << MSR_DWE) |
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(1ull << MSR_DE) |
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(1ull << MSR_FE1) |
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(1ull << MSR_IR) |
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(1ull << MSR_DR);
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pcc->mmu_model = POWERPC_MMU_BOOKE;
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pcc->excp_model = POWERPC_EXCP_BOOKE;
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pcc->bus_model = PPC_FLAGS_INPUT_BookE;
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pcc->bfd_mach = bfd_mach_ppc_403;
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pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
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POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
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}
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static void init_proc_460F(CPUPPCState *env)
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{
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/* Time base */
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gen_tbl(env);
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gen_spr_BookE(env, 0x000000000000FFFFULL);
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gen_spr_440(env);
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gen_spr_usprgh(env);
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/* Processor identification */
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spr_register(env, SPR_BOOKE_PIR, "PIR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_pir,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_IAC3, "IAC3",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_IAC4, "IAC4",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_DVC1, "DVC1",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_DVC2, "DVC2",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_BOOKE_MCSR, "MCSR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_440_CCR1, "CCR1",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* XXX : not implemented */
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spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
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&spr_read_generic, &spr_write_generic,
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&spr_read_generic, &spr_write_generic,
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0x00000000);
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/* Memory management */
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#if !defined(CONFIG_USER_ONLY)
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env->nb_tlb = 64;
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env->nb_ways = 1;
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env->id_tlbs = 0;
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env->tlb_type = TLB_EMB;
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#endif
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init_excp_BookE(env);
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env->dcache_line_size = 32;
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env->icache_line_size = 32;
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/* XXX: TODO: allocate internal IRQ controller */
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SET_FIT_PERIOD(12, 16, 20, 24);
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SET_WDT_PERIOD(20, 24, 28, 32);
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}
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POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
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dc->desc = "PowerPC 460F (guessed)";
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pcc->init_proc = init_proc_460F;
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pcc->check_pow = check_pow_nocheck;
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pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
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PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
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PPC_FLOAT_STFIWX | PPC_MFTB |
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PPC_DCR | PPC_DCRX | PPC_DCRUX |
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PPC_WRTEE | PPC_MFAPIDI |
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PPC_CACHE | PPC_CACHE_ICBI |
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PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
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PPC_MEM_TLBSYNC | PPC_TLBIVA |
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PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
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PPC_440_SPEC;
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pcc->msr_mask = (1ull << MSR_POW) |
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(1ull << MSR_CE) |
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(1ull << MSR_EE) |
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(1ull << MSR_PR) |
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(1ull << MSR_FP) |
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(1ull << MSR_ME) |
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(1ull << MSR_FE0) |
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(1ull << MSR_DWE) |
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(1ull << MSR_DE) |
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(1ull << MSR_FE1) |
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(1ull << MSR_IR) |
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(1ull << MSR_DR);
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pcc->mmu_model = POWERPC_MMU_BOOKE;
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pcc->excp_model = POWERPC_EXCP_BOOKE;
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pcc->bus_model = PPC_FLAGS_INPUT_BookE;
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pcc->bfd_mach = bfd_mach_ppc_403;
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pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
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POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
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}
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static void init_proc_MPC5xx(CPUPPCState *env)
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{
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/* Time base */
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