target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F
As per an unpublished document, in later reversion of chips CP0St_{KX, SX, UX} is not writeable and hardcoded to 1. Without those bits set, kernel is unable to access XKPHYS address segment. So just set them up on CPU reset. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221031132531.18122-2-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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@ -302,6 +302,12 @@ static void mips_cpu_reset(DeviceState *dev)
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env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
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0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
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env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
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if (env->insn_flags & INSN_LOONGSON2F) {
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/* Loongson-2F has those bits hardcoded to 1 */
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env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) |
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(1 << CP0St_UX);
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}
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/*
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* Vectored interrupts not implemented, timer on int 7,
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* no performance counters.
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