Pull request trivial patches 20220426

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2022-04-26 07:54:22 -07:00 · 2022-04-26 07:54:22 -07:00 · 80a172de55
commit 80a172de55
parent a1755db71e 4a89bf188a
6 changed files with 14 additions and 60 deletions
--- a/docs/about/build-platforms.rst
+++ b/docs/about/build-platforms.rst
@ -80,7 +80,7 @@ Ubuntu LTS. Other distros will be assumed to ship similar software versions.
 For FreeBSD and OpenBSD, decisions will be made based on the contents of the
 respective ports repository, while NetBSD will use the pkgsrc repository.

-For macOS, `HomeBrew`_ will be used, although `MacPorts`_ is expected to carry
+For macOS, `Homebrew`_ will be used, although `MacPorts`_ is expected to carry
 similar versions.

 Windows
@ -92,6 +92,6 @@ hosted on Linux (Debian/Fedora).
 The version of the Windows API that's currently targeted is Vista / Server
 2008.

-.. _HomeBrew: https://brew.sh/
+.. _Homebrew: https://brew.sh/
 .. _MacPorts: https://www.macports.org/
 .. _Repology: https://repology.org/
--- a/docs/pcie_sriov.txt
+++ b/docs/pcie_sriov.txt
@ -8,8 +8,8 @@ of a PCI Express device. It allows a single physical function (PF) to appear as
 virtual functions (VFs) for the main purpose of eliminating software
 overhead in I/O from virtual machines.

-Qemu now implements the basic common functionality to enable an emulated device
-to support SR/IOV. Yet no fully implemented devices exists in Qemu, but a
+QEMU now implements the basic common functionality to enable an emulated device
+to support SR/IOV. Yet no fully implemented devices exists in QEMU, but a
 proof-of-concept hack of the Intel igb can be found here:

 git://github.com/knuto/qemu.git sriov_patches_v5
@ -18,7 +18,7 @@ Implementation
 ==============
 Implementing emulation of an SR/IOV capable device typically consists of
 implementing support for two types of device classes; the "normal" physical device
-(PF) and the virtual device (VF). From Qemu's perspective, the VFs are just
+(PF) and the virtual device (VF). From QEMU's perspective, the VFs are just
 like other devices, except that some of their properties are derived from
 the PF.

--- a/hw/rdma/vmw/pvrdma_main.c
+++ b/hw/rdma/vmw/pvrdma_main.c
@ -159,13 +159,13 @@ static void free_dsr(PVRDMADev *dev)
    free_dev_ring(pci_dev, &dev->dsr_info.cq, dev->dsr_info.cq_ring_state);

    rdma_pci_dma_unmap(pci_dev, dev->dsr_info.req,
-                         sizeof(union pvrdma_cmd_req));
+                       sizeof(union pvrdma_cmd_req));

    rdma_pci_dma_unmap(pci_dev, dev->dsr_info.rsp,
-                         sizeof(union pvrdma_cmd_resp));
+                       sizeof(union pvrdma_cmd_resp));

    rdma_pci_dma_unmap(pci_dev, dev->dsr_info.dsr,
-                         sizeof(struct pvrdma_device_shared_region));
+                       sizeof(struct pvrdma_device_shared_region));

    dev->dsr_info.dsr = NULL;
 }
@ -249,7 +249,8 @@ static void init_dsr_dev_caps(PVRDMADev *dev)
 {
    struct pvrdma_device_shared_region *dsr;

-    if (dev->dsr_info.dsr == NULL) {
+    if (!dev->dsr_info.dsr) {
+        /* Buggy or malicious guest driver */
        rdma_error_report("Can't initialized DSR");
        return;
    }
--- a/hw/virtio/trace-events
+++ b/hw/virtio/trace-events
@ -25,6 +25,8 @@ vhost_user_postcopy_waker_nomatch(const char *rb, uint64_t rb_offset) "%s + 0x%"
 # vhost-vdpa.c
 vhost_vdpa_dma_map(void *vdpa, int fd, uint32_t msg_type, uint64_t iova, uint64_t size, uint64_t uaddr, uint8_t perm, uint8_t type) "vdpa:%p fd: %d msg_type: %"PRIu32" iova: 0x%"PRIx64" size: 0x%"PRIx64" uaddr: 0x%"PRIx64" perm: 0x%"PRIx8" type: %"PRIu8
 vhost_vdpa_dma_unmap(void *vdpa, int fd, uint32_t msg_type, uint64_t iova, uint64_t size, uint8_t type) "vdpa:%p fd: %d msg_type: %"PRIu32" iova: 0x%"PRIx64" size: 0x%"PRIx64" type: %"PRIu8
+vhost_vdpa_listener_begin_batch(void *v, int fd, uint32_t msg_type, uint8_t type)  "vdpa:%p fd: %d msg_type: %"PRIu32" type: %"PRIu8
+vhost_vdpa_listener_commit(void *v, int fd, uint32_t msg_type, uint8_t type)  "vdpa:%p fd: %d msg_type: %"PRIu32" type: %"PRIu8
 vhost_vdpa_listener_region_add(void *vdpa, uint64_t iova, uint64_t llend, void *vaddr, bool readonly) "vdpa: %p iova 0x%"PRIx64" llend 0x%"PRIx64" vaddr: %p read-only: %d"
 vhost_vdpa_listener_region_del(void *vdpa, uint64_t iova, uint64_t llend) "vdpa: %p iova 0x%"PRIx64" llend 0x%"PRIx64
 vhost_vdpa_add_status(void *dev, uint8_t status) "dev: %p status: 0x%"PRIx8
--- a/hw/virtio/vhost-vdpa.c
+++ b/hw/virtio/vhost-vdpa.c
@ -129,6 +129,7 @@ static void vhost_vdpa_listener_begin_batch(struct vhost_vdpa *v)
        .iotlb.type = VHOST_IOTLB_BATCH_BEGIN,
    };

+    trace_vhost_vdpa_listener_begin_batch(v, fd, msg.type, msg.iotlb.type);
    if (write(fd, &msg, sizeof(msg)) != sizeof(msg)) {
        error_report("failed to write, fd=%d, errno=%d (%s)",
                     fd, errno, strerror(errno));
@ -163,6 +164,7 @@ static void vhost_vdpa_listener_commit(MemoryListener *listener)
    msg.type = v->msg_type;
    msg.iotlb.type = VHOST_IOTLB_BATCH_END;

+    trace_vhost_vdpa_listener_commit(v, fd, msg.type, msg.iotlb.type);
    if (write(fd, &msg, sizeof(msg)) != sizeof(msg)) {
        error_report("failed to write, fd=%d, errno=%d (%s)",
                     fd, errno, strerror(errno));
--- a/target/mips/TODO
+++ b/target/mips/TODO
@ -1,51 +0,0 @@
-Unsolved issues/bugs in the mips/mipsel backend
-----------------------------------------------
-
-General
-------
- Unimplemented ASEs:
-  - MDMX
-  - SmartMIPS
-  - microMIPS DSP r1 & r2 encodings
- MT ASE only partially implemented and not functional
- Shadow register support only partially implemented,
-  lacks set switching on interrupt/exception.
- 34K ITC not implemented.
- A general lack of documentation, especially for technical internals.
-  Existing documentation is x86-centric.
- Reverse endianness bit not implemented
- The TLB emulation is very inefficient:
-  QEMU's softmmu implements a x86-style MMU, with separate entries
-  for read/write/execute, a TLB index which is just a modulo of the
-  virtual address, and a set of TLBs for each user/kernel/supervisor
-  MMU mode.
-  MIPS has a single entry for read/write/execute and only one MMU mode.
-  But it is fully associative with randomized entry indices, and uses
-  up to 256 ASID tags as additional matching criterion (which roughly
-  equates to 256 MMU modes). It also has a global flag which causes
-  entries to match regardless of ASID.
-  To cope with these differences, QEMU currently flushes the TLB at
-  each ASID change. Using the MMU modes to implement ASIDs hinges on
-  implementing the global bit efficiently.
- save/restore of the CPU state is not implemented (see machine.c).
-
-MIPS64
------
- Userland emulation (both n32 and n64) not functional.
-
-"Generic" 4Kc system emulation
------------------------------
- Doesn't correspond to any real hardware. Should be removed some day,
-  U-Boot is the last remaining user.
-
-PICA 61 system emulation
------------------------
- No framebuffer support yet.
-
-MALTA system emulation
----------------------
- We fake firmware support instead of doing the real thing
- Real firmware (YAMON) falls over when trying to init RAM, presumably
-  due to lacking system controller emulation.
- Bonito system controller not implemented
- MSC1 system controller not implemented