OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/arm: Implement SVE2 TBL, TBX 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-72-richard.henderson@linaro.org
Message-Id: <20200428144352.9275-1-steplong@quicinc.com>
[rth: rearrange the macros a little and rebase]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Stephen Long 2021-05-24 18:03:37 -07:00 committed by Peter Maydell
parent 3358eb3fb7
commit 80a712a2be
4 changed files with 119 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
target/arm/helper-sve.h
View File

@ -661,6 +661,16 @@ DEF_HELPER_FLAGS_4(sve_tbl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_tbl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_tbl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_tbl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_tbl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_tbl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_tbl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_tbx_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_tbx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_tbx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_tbx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_sunpk_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_sunpk_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_sunpk_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)

5
target/arm/sve.decode
View File

@ -558,6 +558,11 @@ TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
# SVE unpack vector elements
UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
# SVE2 Table Lookup (three sources)
TBL_sve2 00000101 .. 1 ..... 001010 ..... ..... @rd_rn_rm
TBX 00000101 .. 1 ..... 001011 ..... ..... @rd_rn_rm
### SVE Permute - Predicates Group
# SVE permute predicate elements

90
target/arm/sve_helper.c
View File

@ -3069,28 +3069,80 @@ void HELPER(sve_rev_d)(void *vd, void *vn, uint32_t desc)
}
}
#define DO_TBL(NAME, TYPE, H) \
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
{ \
intptr_t i, opr_sz = simd_oprsz(desc); \
uintptr_t elem = opr_sz / sizeof(TYPE); \
TYPE *d = vd, *n = vn, *m = vm; \
ARMVectorReg tmp; \
if (unlikely(vd == vn)) { \
n = memcpy(&tmp, vn, opr_sz); \
} \
for (i = 0; i < elem; i++) { \
TYPE j = m[H(i)]; \
d[H(i)] = j < elem ? n[H(j)] : 0; \
} \
typedef void tb_impl_fn(void *, void *, void *, void *, uintptr_t, bool);
static inline void do_tbl1(void *vd, void *vn, void *vm, uint32_t desc,
bool is_tbx, tb_impl_fn *fn)
{
ARMVectorReg scratch;
uintptr_t oprsz = simd_oprsz(desc);
if (unlikely(vd == vn)) {
vn = memcpy(&scratch, vn, oprsz);
}
fn(vd, vn, NULL, vm, oprsz, is_tbx);
}
DO_TBL(sve_tbl_b, uint8_t, H1)
DO_TBL(sve_tbl_h, uint16_t, H2)
DO_TBL(sve_tbl_s, uint32_t, H4)
DO_TBL(sve_tbl_d, uint64_t, )
static inline void do_tbl2(void *vd, void *vn0, void *vn1, void *vm,
uint32_t desc, bool is_tbx, tb_impl_fn *fn)
{
ARMVectorReg scratch;
uintptr_t oprsz = simd_oprsz(desc);
#undef TBL
if (unlikely(vd == vn0)) {
vn0 = memcpy(&scratch, vn0, oprsz);
if (vd == vn1) {
vn1 = vn0;
}
} else if (unlikely(vd == vn1)) {
vn1 = memcpy(&scratch, vn1, oprsz);
}
fn(vd, vn0, vn1, vm, oprsz, is_tbx);
}
#define DO_TB(SUFF, TYPE, H) \
static inline void do_tb_##SUFF(void *vd, void *vt0, void *vt1, \
void *vm, uintptr_t oprsz, bool is_tbx) \
{ \
TYPE *d = vd, *tbl0 = vt0, *tbl1 = vt1, *indexes = vm; \
uintptr_t i, nelem = oprsz / sizeof(TYPE); \
for (i = 0; i < nelem; ++i) { \
TYPE index = indexes[H1(i)], val = 0; \
if (index < nelem) { \
val = tbl0[H(index)]; \
} else { \
index -= nelem; \
if (tbl1 && index < nelem) { \
val = tbl1[H(index)]; \
} else if (is_tbx) { \
continue; \
} \
} \
d[H(i)] = val; \
} \
} \
void HELPER(sve_tbl_##SUFF)(void *vd, void *vn, void *vm, uint32_t desc) \
{ \
do_tbl1(vd, vn, vm, desc, false, do_tb_##SUFF); \
} \
void HELPER(sve2_tbl_##SUFF)(void *vd, void *vn0, void *vn1, \
void *vm, uint32_t desc) \
{ \
do_tbl2(vd, vn0, vn1, vm, desc, false, do_tb_##SUFF); \
} \
void HELPER(sve2_tbx_##SUFF)(void *vd, void *vn, void *vm, uint32_t desc) \
{ \
do_tbl1(vd, vn, vm, desc, true, do_tb_##SUFF); \
}
DO_TB(b, uint8_t, H1)
DO_TB(h, uint16_t, H2)
DO_TB(s, uint32_t, H4)
DO_TB(d, uint64_t, )
#undef DO_TB
#define DO_UNPK(NAME, TYPED, TYPES, HD, HS) \
void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \

33
target/arm/translate-sve.c
View File

@ -2417,6 +2417,39 @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
return true;
}
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
{
static gen_helper_gvec_4 * const fns[4] = {
gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h,
gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d
};
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
if (sve_access_check(s)) {
gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
(a->rn + 1) % 32, a->rm, 0);
}
return true;
}
static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
{
static gen_helper_gvec_3 * const fns[4] = {
gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d
};
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
if (sve_access_check(s)) {
gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
}
return true;
}
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
{
static gen_helper_gvec_2 * const fns[4][2] = {