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target/mips/tx79: Introduce SQ opcode (Store Quadword)

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Introduce the SQ opcode (Store Quadword).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-27-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-02-13 14:47:47 +01:00
parent aaaa82a9f9
commit 80ad630357
2 changed files with 28 additions and 0 deletions
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1
target/mips/tcg/tx79.decode
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@ -70,3 +70,4 @@ PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd
# SPECIAL
LQ 011110 ..... ..... ................ @ldst
SQ 011111 ..... ..... ................ @ldst

27
target/mips/tcg/tx79_translate.c
View File

@ -369,6 +369,33 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a)
return true;
}
static bool trans_SQ(DisasContext *ctx, arg_itype *a)
{
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv addr = tcg_temp_new();
gen_base_offset_addr(ctx, addr, a->base, a->offset);
/*
* Clear least-significant four bits of the effective
* address, effectively creating an aligned address.
*/
tcg_gen_andi_tl(addr, addr, ~0xf);
/* Lower half */
gen_load_gpr(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
tcg_temp_free(addr);
tcg_temp_free(t0);
return true;
}
/*
* Multiply and Divide (19 instructions)
* -------------------------------------