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hw/mips/gt64xxx_pci: Align the pci0-mem size

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One byte is missing, use an aligned size.

    (qemu) info mtree
    memory-region: pci0-mem
      0000000000000000-00000000fffffffe (prio 0, i/o): pci0-mem
                                      ^

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-8-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2019-06-25 00:28:41 +02:00 committed by Aleksandar Markovic
parent ab6bff424f
commit 8110b2bf7e
1 changed files with 2 additions and 1 deletions
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3
hw/mips/gt64xxx_pci.c
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@ -23,6 +23,7 @@
*/ */
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/log.h" #include "qemu/log.h"
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/mips/mips.h" #include "hw/mips/mips.h"
@ -1201,7 +1202,7 @@ PCIBus *gt64120_register(qemu_irq *pic)
dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE); dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
d = GT64120_PCI_HOST_BRIDGE(dev); d = GT64120_PCI_HOST_BRIDGE(dev);
phb = PCI_HOST_BRIDGE(dev); phb = PCI_HOST_BRIDGE(dev);
memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX); memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
phb->bus = pci_register_root_bus(dev, "pci", phb->bus = pci_register_root_bus(dev, "pci",
gt64120_pci_set_irq, gt64120_pci_map_irq, gt64120_pci_set_irq, gt64120_pci_map_irq,