Move sun4c to its own hwdef (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5549 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
43d7ac4e74
commit
8137cde8f9
480
hw/sun4m.c
480
hw/sun4m.c
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@ -88,7 +88,7 @@
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#define MAX_CPUS 16
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#define MAX_PILS 16
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struct hwdef {
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struct sun4m_hwdef {
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target_phys_addr_t iommu_base, slavio_base;
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
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target_phys_addr_t serial_base, fd_base;
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@ -96,7 +96,6 @@ struct hwdef {
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
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target_phys_addr_t ecc_base;
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uint32_t ecc_version;
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target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
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long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but master interrupt controller
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// register bit numbers
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@ -131,6 +130,25 @@ struct sun4d_hwdef {
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const char * const default_cpu_model;
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};
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struct sun4c_hwdef {
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target_phys_addr_t iommu_base, slavio_base;
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target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
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target_phys_addr_t serial_base, fd_base;
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target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
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target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
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long vram_size, nvram_size;
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// IRQ numbers are not PIL ones, but master interrupt controller
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// register bit numbers
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int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
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int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
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uint8_t nvram_machine_id;
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uint16_t machine_id;
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uint32_t iommu_version;
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uint32_t intbit_to_level[32];
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uint64_t max_mem;
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const char * const default_cpu_model;
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};
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int DMA_get_channel_mode (int nchan)
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{
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return 0;
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@ -395,7 +413,7 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename,
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return kernel_size;
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}
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static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
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static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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const char *boot_device,
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DisplayState *ds, const char *kernel_filename,
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const char *kernel_cmdline,
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@ -584,158 +602,6 @@ static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
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fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
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}
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static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
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const char *boot_device,
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DisplayState *ds, const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env;
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unsigned int i;
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void *iommu, *espdma, *ledma, *main_esp, *nvram;
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qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
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qemu_irq *esp_reset, *le_reset;
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qemu_irq *fdc_tc;
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unsigned long prom_offset, kernel_size;
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int ret;
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char buf[1024];
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BlockDriverState *fd[MAX_FD];
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int drive_index;
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void *fw_cfg;
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/* init CPU */
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if (!cpu_model)
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cpu_model = hwdef->default_cpu_model;
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
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exit(1);
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}
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cpu_sparc_set_id(env, 0);
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qemu_register_reset(main_cpu_reset, env);
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cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
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env->prom_addr = hwdef->slavio_base;
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/* allocate RAM */
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if ((uint64_t)RAM_size > hwdef->max_mem) {
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fprintf(stderr,
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"qemu: Too much memory for this machine: %d, maximum %d\n",
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(unsigned int)(RAM_size / (1024 * 1024)),
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(unsigned int)(hwdef->max_mem / (1024 * 1024)));
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exit(1);
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}
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cpu_register_physical_memory(0, RAM_size, 0);
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/* load boot prom */
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prom_offset = RAM_size + hwdef->vram_size;
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cpu_register_physical_memory(hwdef->slavio_base,
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(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
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TARGET_PAGE_MASK,
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prom_offset | IO_MEM_ROM);
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if (bios_name == NULL)
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bios_name = PROM_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
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if (ret < 0 || ret > PROM_SIZE_MAX)
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ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
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if (ret < 0 || ret > PROM_SIZE_MAX) {
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fprintf(stderr, "qemu: could not load prom '%s'\n",
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buf);
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exit(1);
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}
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prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
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/* set up devices */
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slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
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&slavio_irq, cpu_irqs);
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iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
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slavio_irq[hwdef->me_irq]);
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espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
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iommu, &espdma_irq, &esp_reset);
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ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
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slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
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&le_reset);
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if (graphic_depth != 8 && graphic_depth != 24) {
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fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
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exit (1);
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}
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tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
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hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "lance") == 0) {
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lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
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} else if (strcmp(nd_table[0].model, "?") == 0) {
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fprintf(stderr, "qemu: Supported NICs: lance\n");
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exit (1);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
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hwdef->nvram_size, 2);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
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nographic);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
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serial_hds[1], serial_hds[0]);
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slavio_misc = slavio_misc_init(0, hwdef->apc_base,
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hwdef->aux1_base, hwdef->aux2_base,
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slavio_irq[hwdef->me_irq], env, &fdc_tc);
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if (hwdef->fd_base != (target_phys_addr_t)-1) {
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/* there is zero or one floppy drive */
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fd[1] = fd[0] = NULL;
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drive_index = drive_get_index(IF_FLOPPY, 0, 0);
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if (drive_index != -1)
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fd[0] = drives_table[drive_index].bdrv;
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sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
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fdc_tc);
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}
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if (drive_get_max_bus(IF_SCSI) > 0) {
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fprintf(stderr, "qemu: too many SCSI bus\n");
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exit(1);
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}
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main_esp = esp_init(hwdef->esp_base, 2,
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espdma_memory_read, espdma_memory_write,
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espdma, *espdma_irq, esp_reset);
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for (i = 0; i < ESP_MAX_DEVS; i++) {
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drive_index = drive_get_index(IF_SCSI, 0, i);
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if (drive_index == -1)
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continue;
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esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
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}
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kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
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RAM_size);
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nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
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boot_device, RAM_size, kernel_size, graphic_width,
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graphic_height, graphic_depth, hwdef->nvram_machine_id,
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"Sun4c");
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fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
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fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
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}
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enum {
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ss2_id = 0,
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ss5_id = 32,
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@ -751,7 +617,7 @@ enum {
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ss2000_id,
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};
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static const struct hwdef hwdefs[] = {
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static const struct sun4m_hwdef sun4m_hwdefs[] = {
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/* SS-5 */
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{
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.iommu_base = 0x10000000,
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@ -772,8 +638,6 @@ static const struct hwdef hwdefs[] = {
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -816,8 +680,6 @@ static const struct hwdef hwdefs[] = {
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.aux2_base = 0xff1a01000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x10000000, // version 0, implementation 1
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -861,8 +723,6 @@ static const struct hwdef hwdefs[] = {
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.aux2_base = 0xff1a01000ULL, // XXX should not exist
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x00000000, // version 0, implementation 0
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -906,8 +766,6 @@ static const struct hwdef hwdefs[] = {
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.aux2_base = 0xff1a01000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x20000000, // version 0, implementation 2
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -930,42 +788,6 @@ static const struct hwdef hwdefs[] = {
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.max_mem = 0xf00000000ULL,
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.default_cpu_model = "TI SuperSparc II",
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},
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/* SS-2 */
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{
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.iommu_base = 0xf8000000,
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.tcx_base = 0xfe000000,
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.cs_base = -1,
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.slavio_base = 0xf6000000,
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.ms_kb_base = 0xf0000000,
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.serial_base = 0xf1000000,
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.nvram_base = 0xf2000000,
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.fd_base = 0xf7200000,
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.counter_base = -1,
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.intctl_base = -1,
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.dma_base = 0xf8400000,
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.esp_base = 0xf8800000,
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.le_base = 0xf8c00000,
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.apc_base = -1,
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.aux1_base = 0xf7400003,
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.aux2_base = -1,
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.sun4c_intctl_base = 0xf5000000,
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.sun4c_counter_base = 0xf3000000,
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.vram_size = 0x00100000,
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.nvram_size = 0x800,
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.esp_irq = 2,
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.le_irq = 3,
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.clock_irq = 5,
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.clock1_irq = 7,
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.ms_kb_irq = 1,
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.ser_irq = 1,
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.fd_irq = 1,
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.me_irq = 1,
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.cs_irq = -1,
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.nvram_machine_id = 0x55,
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.machine_id = ss2_id,
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.max_mem = 0x10000000,
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.default_cpu_model = "Cypress CY7C601",
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},
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/* Voyager */
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{
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.iommu_base = 0x10000000,
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@ -986,8 +808,6 @@ static const struct hwdef hwdefs[] = {
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -1029,8 +849,6 @@ static const struct hwdef hwdefs[] = {
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -1072,8 +890,6 @@ static const struct hwdef hwdefs[] = {
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -1115,8 +931,6 @@ static const struct hwdef hwdefs[] = {
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -1158,8 +972,6 @@ static const struct hwdef hwdefs[] = {
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.ecc_base = -1,
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.sun4c_intctl_base = -1,
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.sun4c_counter_base = -1,
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.vram_size = 0x00100000,
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.nvram_size = 0x2000,
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.esp_irq = 18,
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@ -1189,7 +1001,7 @@ static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
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sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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@ -1199,7 +1011,7 @@ static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
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sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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@ -1210,7 +1022,7 @@ static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
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const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
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sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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@ -1220,17 +1032,7 @@ static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
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kernel_cmdline, initrd_filename, cpu_model);
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}
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/* SPARCstation 2 hardware initialisation */
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static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
|
||||
const char *boot_device, DisplayState *ds,
|
||||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
|
||||
sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
|
|
@ -1240,7 +1042,7 @@ static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
|
|||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
|
||||
sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
|
|
@ -1250,7 +1052,7 @@ static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
|
|||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
|
||||
sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
|
|
@ -1260,7 +1062,7 @@ static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
|
|||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
|
||||
sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
|
|
@ -1270,7 +1072,7 @@ static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
|
|||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
|
||||
sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
|
|
@ -1280,7 +1082,7 @@ static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
|
|||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
|
||||
sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
|
|
@ -1324,16 +1126,6 @@ QEMUMachine ss20_machine = {
|
|||
.max_cpus = 16,
|
||||
};
|
||||
|
||||
QEMUMachine ss2_machine = {
|
||||
.name = "SS-2",
|
||||
.desc = "Sun4c platform, SPARCstation 2",
|
||||
.init = ss2_init,
|
||||
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
|
||||
.nodisk_ok = 1,
|
||||
.use_scsi = 1,
|
||||
.max_cpus = 16,
|
||||
};
|
||||
|
||||
QEMUMachine voyager_machine = {
|
||||
.name = "Voyager",
|
||||
.desc = "Sun4m platform, SPARCstation Voyager",
|
||||
|
|
@ -1642,3 +1434,213 @@ QEMUMachine ss2000_machine = {
|
|||
.use_scsi = 1,
|
||||
.max_cpus = 16,
|
||||
};
|
||||
|
||||
static const struct sun4c_hwdef sun4c_hwdefs[] = {
|
||||
/* SS-2 */
|
||||
{
|
||||
.iommu_base = 0xf8000000,
|
||||
.tcx_base = 0xfe000000,
|
||||
.cs_base = -1,
|
||||
.slavio_base = 0xf6000000,
|
||||
.intctl_base = 0xf5000000,
|
||||
.counter_base = 0xf3000000,
|
||||
.ms_kb_base = 0xf0000000,
|
||||
.serial_base = 0xf1000000,
|
||||
.nvram_base = 0xf2000000,
|
||||
.fd_base = 0xf7200000,
|
||||
.dma_base = 0xf8400000,
|
||||
.esp_base = 0xf8800000,
|
||||
.le_base = 0xf8c00000,
|
||||
.apc_base = -1,
|
||||
.aux1_base = 0xf7400003,
|
||||
.aux2_base = -1,
|
||||
.vram_size = 0x00100000,
|
||||
.nvram_size = 0x800,
|
||||
.esp_irq = 2,
|
||||
.le_irq = 3,
|
||||
.clock_irq = 5,
|
||||
.clock1_irq = 7,
|
||||
.ms_kb_irq = 1,
|
||||
.ser_irq = 1,
|
||||
.fd_irq = 1,
|
||||
.me_irq = 1,
|
||||
.cs_irq = -1,
|
||||
.nvram_machine_id = 0x55,
|
||||
.machine_id = ss2_id,
|
||||
.max_mem = 0x10000000,
|
||||
.default_cpu_model = "Cypress CY7C601",
|
||||
},
|
||||
};
|
||||
|
||||
static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
|
||||
const char *boot_device,
|
||||
DisplayState *ds, const char *kernel_filename,
|
||||
const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
CPUState *env;
|
||||
unsigned int i;
|
||||
void *iommu, *espdma, *ledma, *main_esp, *nvram;
|
||||
qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
|
||||
qemu_irq *esp_reset, *le_reset;
|
||||
qemu_irq *fdc_tc;
|
||||
unsigned long prom_offset, kernel_size;
|
||||
int ret;
|
||||
char buf[1024];
|
||||
BlockDriverState *fd[MAX_FD];
|
||||
int drive_index;
|
||||
void *fw_cfg;
|
||||
|
||||
/* init CPU */
|
||||
if (!cpu_model)
|
||||
cpu_model = hwdef->default_cpu_model;
|
||||
|
||||
env = cpu_init(cpu_model);
|
||||
if (!env) {
|
||||
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
cpu_sparc_set_id(env, 0);
|
||||
|
||||
qemu_register_reset(main_cpu_reset, env);
|
||||
cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
|
||||
env->prom_addr = hwdef->slavio_base;
|
||||
|
||||
/* allocate RAM */
|
||||
if ((uint64_t)RAM_size > hwdef->max_mem) {
|
||||
fprintf(stderr,
|
||||
"qemu: Too much memory for this machine: %d, maximum %d\n",
|
||||
(unsigned int)(RAM_size / (1024 * 1024)),
|
||||
(unsigned int)(hwdef->max_mem / (1024 * 1024)));
|
||||
exit(1);
|
||||
}
|
||||
cpu_register_physical_memory(0, RAM_size, 0);
|
||||
|
||||
/* load boot prom */
|
||||
prom_offset = RAM_size + hwdef->vram_size;
|
||||
cpu_register_physical_memory(hwdef->slavio_base,
|
||||
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
|
||||
TARGET_PAGE_MASK,
|
||||
prom_offset | IO_MEM_ROM);
|
||||
|
||||
if (bios_name == NULL)
|
||||
bios_name = PROM_FILENAME;
|
||||
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
|
||||
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
|
||||
if (ret < 0 || ret > PROM_SIZE_MAX)
|
||||
ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
|
||||
if (ret < 0 || ret > PROM_SIZE_MAX) {
|
||||
fprintf(stderr, "qemu: could not load prom '%s'\n",
|
||||
buf);
|
||||
exit(1);
|
||||
}
|
||||
prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
|
||||
|
||||
/* set up devices */
|
||||
slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
|
||||
&slavio_irq, cpu_irqs);
|
||||
|
||||
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
|
||||
slavio_irq[hwdef->me_irq]);
|
||||
|
||||
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
|
||||
iommu, &espdma_irq, &esp_reset);
|
||||
|
||||
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
||||
slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
|
||||
&le_reset);
|
||||
|
||||
if (graphic_depth != 8 && graphic_depth != 24) {
|
||||
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
||||
exit (1);
|
||||
}
|
||||
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
|
||||
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
|
||||
|
||||
if (nd_table[0].model == NULL
|
||||
|| strcmp(nd_table[0].model, "lance") == 0) {
|
||||
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
|
||||
} else if (strcmp(nd_table[0].model, "?") == 0) {
|
||||
fprintf(stderr, "qemu: Supported NICs: lance\n");
|
||||
exit (1);
|
||||
} else {
|
||||
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
|
||||
exit (1);
|
||||
}
|
||||
|
||||
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
|
||||
hwdef->nvram_size, 2);
|
||||
|
||||
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
|
||||
nographic);
|
||||
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
|
||||
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
|
||||
slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
|
||||
serial_hds[1], serial_hds[0]);
|
||||
|
||||
slavio_misc = slavio_misc_init(0, hwdef->apc_base,
|
||||
hwdef->aux1_base, hwdef->aux2_base,
|
||||
slavio_irq[hwdef->me_irq], env, &fdc_tc);
|
||||
|
||||
if (hwdef->fd_base != (target_phys_addr_t)-1) {
|
||||
/* there is zero or one floppy drive */
|
||||
fd[1] = fd[0] = NULL;
|
||||
drive_index = drive_get_index(IF_FLOPPY, 0, 0);
|
||||
if (drive_index != -1)
|
||||
fd[0] = drives_table[drive_index].bdrv;
|
||||
|
||||
sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
|
||||
fdc_tc);
|
||||
}
|
||||
|
||||
if (drive_get_max_bus(IF_SCSI) > 0) {
|
||||
fprintf(stderr, "qemu: too many SCSI bus\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
main_esp = esp_init(hwdef->esp_base, 2,
|
||||
espdma_memory_read, espdma_memory_write,
|
||||
espdma, *espdma_irq, esp_reset);
|
||||
|
||||
for (i = 0; i < ESP_MAX_DEVS; i++) {
|
||||
drive_index = drive_get_index(IF_SCSI, 0, i);
|
||||
if (drive_index == -1)
|
||||
continue;
|
||||
esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
|
||||
}
|
||||
|
||||
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
|
||||
RAM_size);
|
||||
|
||||
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
||||
boot_device, RAM_size, kernel_size, graphic_width,
|
||||
graphic_height, graphic_depth, hwdef->nvram_machine_id,
|
||||
"Sun4c");
|
||||
|
||||
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
|
||||
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
||||
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
||||
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
|
||||
}
|
||||
|
||||
/* SPARCstation 2 hardware initialisation */
|
||||
static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
|
||||
const char *boot_device, DisplayState *ds,
|
||||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
{
|
||||
sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
|
||||
kernel_cmdline, initrd_filename, cpu_model);
|
||||
}
|
||||
|
||||
QEMUMachine ss2_machine = {
|
||||
.name = "SS-2",
|
||||
.desc = "Sun4c platform, SPARCstation 2",
|
||||
.init = ss2_init,
|
||||
.ram_require = PROM_SIZE_MAX + TCX_SIZE,
|
||||
.nodisk_ok = 1,
|
||||
.use_scsi = 1,
|
||||
.max_cpus = 16,
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue