target-mips: Correct the writes to Status and Cause registers via gdbstub
Make writes to CP0.Status and CP0.Cause have the same effect as executing corresponding MTC0 instructions would in Kernel Mode. Also ignore writes in the user emulation mode. Currently for requests from the GDB stub we write all the bits across both registers, ignoring any read-only locations, and do not synchronise the environment to evaluate side effects. We also write these registers in the user emulation mode even though a real kernel presents them as read only. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Maciej W. Rozycki
Leon Alrae
parent
f88f79ec9d
commit
81a423e6c6
@ -904,4 +904,93 @@ static inline void compute_hflags(CPUMIPSState *env)
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}
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}
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#ifndef CONFIG_USER_ONLY
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/* Called for updates to CP0_Status. */
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static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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uint32_t cu, mx, asid, ksu;
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uint32_t mask = ((1 << CP0TCSt_TCU3)
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| (1 << CP0TCSt_TCU2)
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| (1 << CP0TCSt_TCU1)
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| (1 << CP0TCSt_TCU0)
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| (1 << CP0TCSt_TMX)
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| (3 << CP0TCSt_TKSU)
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| (0xff << CP0TCSt_TASID));
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cu = (v >> CP0St_CU0) & 0xf;
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mx = (v >> CP0St_MX) & 0x1;
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ksu = (v >> CP0St_KSU) & 0x3;
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asid = env->CP0_EntryHi & 0xff;
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tcstatus = cu << CP0TCSt_TCU0;
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tcstatus |= mx << CP0TCSt_TMX;
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tcstatus |= ksu << CP0TCSt_TKSU;
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tcstatus |= asid;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~mask;
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*tcst |= tcstatus;
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compute_hflags(cpu);
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}
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static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = env->CP0_Status_rw_bitmask;
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if (env->insn_flags & ISA_MIPS32R6) {
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bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
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if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
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mask &= ~(3 << CP0St_KSU);
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}
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mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
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}
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env->CP0_Status = (env->CP0_Status & ~mask) | (val & mask);
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if (env->CP0_Config3 & (1 << CP0C3_MT)) {
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sync_c0_status(env, env, env->current_tc);
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} else {
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compute_hflags(env);
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}
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}
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static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = 0x00C00300;
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uint32_t old = env->CP0_Cause;
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int i;
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if (env->insn_flags & ISA_MIPS32R2) {
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mask |= 1 << CP0Ca_DC;
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}
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if (env->insn_flags & ISA_MIPS32R6) {
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mask &= ~((1 << CP0Ca_WP) & val);
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}
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env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
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if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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cpu_mips_stop_count(env);
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} else {
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cpu_mips_start_count(env);
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}
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}
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/* Set/reset software interrupts */
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for (i = 0 ; i < 2 ; i++) {
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if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
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cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
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}
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}
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}
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#endif
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#endif /* !defined (__MIPS_CPU_H__) */
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@ -112,7 +112,9 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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}
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switch (n) {
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case 32:
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env->CP0_Status = tmp;
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#ifndef CONFIG_USER_ONLY
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cpu_mips_store_status(env, tmp);
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#endif
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break;
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case 33:
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env->active_tc.LO[0] = tmp;
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@ -124,7 +126,9 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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env->CP0_BadVAddr = tmp;
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break;
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case 36:
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env->CP0_Cause = tmp;
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#ifndef CONFIG_USER_ONLY
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cpu_mips_store_cause(env, tmp);
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#endif
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break;
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case 37:
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env->active_tc.PC = tmp & ~(target_ulong)1;
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@ -625,40 +625,9 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
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These helper call synchronizes the regs for a given cpu. */
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/* Called for updates to CP0_Status. */
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static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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uint32_t cu, mx, asid, ksu;
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uint32_t mask = ((1 << CP0TCSt_TCU3)
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| (1 << CP0TCSt_TCU2)
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| (1 << CP0TCSt_TCU1)
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| (1 << CP0TCSt_TCU0)
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| (1 << CP0TCSt_TMX)
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| (3 << CP0TCSt_TKSU)
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| (0xff << CP0TCSt_TASID));
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cu = (v >> CP0St_CU0) & 0xf;
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mx = (v >> CP0St_MX) & 0x1;
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ksu = (v >> CP0St_KSU) & 0x3;
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asid = env->CP0_EntryHi & 0xff;
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tcstatus = cu << CP0TCSt_TCU0;
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tcstatus |= mx << CP0TCSt_TMX;
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tcstatus |= ksu << CP0TCSt_TKSU;
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tcstatus |= asid;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~mask;
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*tcst |= tcstatus;
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compute_hflags(cpu);
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}
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/* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
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/* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
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int tc); */
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/* Called for updates to CP0_TCStatus. */
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static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
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@ -1420,25 +1389,10 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
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{
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MIPSCPU *cpu = mips_env_get_cpu(env);
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uint32_t val, old;
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uint32_t mask = env->CP0_Status_rw_bitmask;
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if (env->insn_flags & ISA_MIPS32R6) {
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bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
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if (has_supervisor && extract32(arg1, CP0St_KSU, 2) == 0x3) {
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mask &= ~(3 << CP0St_KSU);
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}
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mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & arg1);
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}
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val = arg1 & mask;
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old = env->CP0_Status;
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env->CP0_Status = (env->CP0_Status & ~mask) | val;
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if (env->CP0_Config3 & (1 << CP0C3_MT)) {
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sync_c0_status(env, env, env->current_tc);
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} else {
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compute_hflags(env);
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}
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cpu_mips_store_status(env, arg1);
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val = env->CP0_Status;
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if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
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qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
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@ -1477,40 +1431,9 @@ void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
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env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
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}
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static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
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{
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uint32_t mask = 0x00C00300;
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uint32_t old = cpu->CP0_Cause;
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int i;
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if (cpu->insn_flags & ISA_MIPS32R2) {
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mask |= 1 << CP0Ca_DC;
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}
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if (cpu->insn_flags & ISA_MIPS32R6) {
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mask &= ~((1 << CP0Ca_WP) & arg1);
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}
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cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
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if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
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if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
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cpu_mips_stop_count(cpu);
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} else {
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cpu_mips_start_count(cpu);
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}
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}
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/* Set/reset software interrupts */
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for (i = 0 ; i < 2 ; i++) {
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if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
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cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
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}
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}
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}
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void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
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{
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mtc0_cause(env, arg1);
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cpu_mips_store_cause(env, arg1);
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}
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void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
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@ -1518,7 +1441,7 @@ void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
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int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
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CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
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mtc0_cause(other, arg1);
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cpu_mips_store_cause(other, arg1);
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}
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target_ulong helper_mftc0_epc(CPUMIPSState *env)
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