OpenE2K/qemu-e2k
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Use andc, orc, nor and nand

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Also fix which argument gets negated in fandnot[12] and fornot[12]


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5662 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-11-09 19:50:37 +00:00
parent 741a7444a3
commit 81b5b816e2
1 changed files with 36 additions and 52 deletions
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88
target-sparc/translate.c
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@ -3079,14 +3079,12 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
break; break;
case 0x5: case 0x5:
tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
if (xop & 0x10) if (xop & 0x10)
gen_op_logic_cc(cpu_dst); gen_op_logic_cc(cpu_dst);
break; break;
case 0x6: case 0x6:
tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1); tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
if (xop & 0x10) if (xop & 0x10)
gen_op_logic_cc(cpu_dst); gen_op_logic_cc(cpu_dst);
break; break;
@ -3907,31 +3905,26 @@ static void disas_sparc_insn(DisasContext * dc)
break; break;
case 0x062: /* VIS I fnor */ case 0x062: /* VIS I fnor */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
cpu_fpr[DFPREG(rs2)]); cpu_fpr[DFPREG(rs2)]);
tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], cpu_fpr[DFPREG(rs2) + 1]);
cpu_fpr[DFPREG(rs2) + 1]);
tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1);
break; break;
case 0x063: /* VIS I fnors */ case 0x063: /* VIS I fnors */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_or_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
break; break;
case 0x064: /* VIS I fandnot2 */ case 0x064: /* VIS I fandnot2 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, cpu_fpr[DFPREG(rs2)]);
cpu_fpr[DFPREG(rs2)]); tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); cpu_fpr[DFPREG(rs1) + 1],
tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1]);
cpu_fpr[DFPREG(rs2) + 1]);
break; break;
case 0x065: /* VIS I fandnot2s */ case 0x065: /* VIS I fandnot2s */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1); tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]);
break; break;
case 0x066: /* VIS I fnot2 */ case 0x066: /* VIS I fnot2 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
@ -3946,17 +3939,15 @@ static void disas_sparc_insn(DisasContext * dc)
break; break;
case 0x068: /* VIS I fandnot1 */ case 0x068: /* VIS I fandnot1 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, cpu_fpr[DFPREG(rs1)]);
cpu_fpr[DFPREG(rs1)]); tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); cpu_fpr[DFPREG(rs2) + 1],
tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1]);
cpu_fpr[DFPREG(rs1) + 1]);
break; break;
case 0x069: /* VIS I fandnot1s */ case 0x069: /* VIS I fandnot1s */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]);
tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
break; break;
case 0x06a: /* VIS I fnot1 */ case 0x06a: /* VIS I fnot1 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
@ -3983,17 +3974,14 @@ static void disas_sparc_insn(DisasContext * dc)
break; break;
case 0x06e: /* VIS I fnand */ case 0x06e: /* VIS I fnand */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
cpu_fpr[DFPREG(rs2)]); cpu_fpr[DFPREG(rs2)]);
tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], cpu_fpr[DFPREG(rs2) + 1]);
cpu_fpr[DFPREG(rs2) + 1]);
tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1);
break; break;
case 0x06f: /* VIS I fnands */ case 0x06f: /* VIS I fnands */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_and_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
break; break;
case 0x070: /* VIS I fand */ case 0x070: /* VIS I fand */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
@ -4033,17 +4021,15 @@ static void disas_sparc_insn(DisasContext * dc)
break; break;
case 0x076: /* VIS I fornot2 */ case 0x076: /* VIS I fornot2 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, cpu_fpr[DFPREG(rs2)]);
cpu_fpr[DFPREG(rs2)]); tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); cpu_fpr[DFPREG(rs1) + 1],
tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1]);
cpu_fpr[DFPREG(rs2) + 1]);
break; break;
case 0x077: /* VIS I fornot2s */ case 0x077: /* VIS I fornot2s */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1); tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]);
break; break;
case 0x078: /* VIS I fsrc2 */ case 0x078: /* VIS I fsrc2 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
@ -4056,17 +4042,15 @@ static void disas_sparc_insn(DisasContext * dc)
break; break;
case 0x07a: /* VIS I fornot1 */ case 0x07a: /* VIS I fornot1 */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, cpu_fpr[DFPREG(rs1)]);
cpu_fpr[DFPREG(rs1)]); tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); cpu_fpr[DFPREG(rs2) + 1],
tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1]);
cpu_fpr[DFPREG(rs1) + 1]);
break; break;
case 0x07b: /* VIS I fornot1s */ case 0x07b: /* VIS I fornot1s */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1); tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]);
tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
break; break;
case 0x07c: /* VIS I for */ case 0x07c: /* VIS I for */
CHECK_FPU_FEATURE(dc, VIS1); CHECK_FPU_FEATURE(dc, VIS1);