target/cris: Reindent mmu.c
Fix all of the coding style errors in this file at once. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -43,8 +43,9 @@ static inline unsigned int compute_polynom(unsigned int sr)
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unsigned int f;
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f = 0;
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for (i = 0; i < 16; i++)
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for (i = 0; i < 16; i++) {
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f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
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}
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return f;
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}
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@ -75,10 +76,11 @@ static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
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uint32_t base;
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int i;
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if (seg < 8)
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if (seg < 8) {
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base = env->sregs[SFR_RW_MM_KBASE_LO];
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else
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} else {
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base = env->sregs[SFR_RW_MM_KBASE_HI];
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}
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i = seg & 7;
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base >>= i * 4;
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@ -87,6 +89,7 @@ static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
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base <<= 28;
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return base;
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}
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/* Used by the tlb decoder. */
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#define EXTRACT_FIELD(src, start, end) \
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(((src) >> start) & ((1 << (end - start + 1)) - 1))
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@ -149,10 +152,17 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
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pid = env->pregs[PR_PID] & 0xff;
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switch (rw) {
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case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
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case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
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case 2:
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rwcause = CRIS_MMU_ERR_EXEC;
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mmu = 0;
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break;
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case 1:
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rwcause = CRIS_MMU_ERR_WRITE;
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break;
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default:
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case 0: rwcause = CRIS_MMU_ERR_READ; break;
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case 0:
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rwcause = CRIS_MMU_ERR_READ;
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break;
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}
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/* I exception vectors 4 - 7, D 8 - 11. */
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@ -160,25 +170,12 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
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vpage = vaddr >> 13;
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/* We know the index which to check on each set.
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Scan both I and D. */
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#if 0
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for (set = 0; set < 4; set++) {
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for (idx = 0; idx < 16; idx++) {
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lo = env->tlbsets[mmu][set][idx].lo;
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hi = env->tlbsets[mmu][set][idx].hi;
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tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
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set, idx, hi, lo, tlb_vpn, tlb_pfn);
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}
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}
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#endif
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/*
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* We know the index which to check on each set.
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* Scan both I and D.
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*/
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idx = vpage & 15;
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for (set = 0; set < 4; set++)
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{
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for (set = 0; set < 4; set++) {
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lo = env->tlbsets[mmu][set][idx].lo;
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hi = env->tlbsets[mmu][set][idx].hi;
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@ -188,8 +185,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
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D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
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mmu, set, idx, tlb_vpn, vpage, lo, hi);
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if ((tlb_g || (tlb_pid == pid))
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&& tlb_vpn == vpage) {
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if ((tlb_g || (tlb_pid == pid)) && tlb_vpn == vpage) {
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match = 1;
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break;
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}
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@ -209,14 +205,14 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
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tlb_x = EXTRACT_FIELD(lo, 0, 0);
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/*
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set_exception_vector(0x04, i_mmu_refill);
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set_exception_vector(0x05, i_mmu_invalid);
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set_exception_vector(0x06, i_mmu_access);
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set_exception_vector(0x07, i_mmu_execute);
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set_exception_vector(0x08, d_mmu_refill);
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set_exception_vector(0x09, d_mmu_invalid);
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set_exception_vector(0x0a, d_mmu_access);
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set_exception_vector(0x0b, d_mmu_write);
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* set_exception_vector(0x04, i_mmu_refill);
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* set_exception_vector(0x05, i_mmu_invalid);
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* set_exception_vector(0x06, i_mmu_access);
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* set_exception_vector(0x07, i_mmu_execute);
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* set_exception_vector(0x08, d_mmu_refill);
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* set_exception_vector(0x09, d_mmu_invalid);
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* set_exception_vector(0x0a, d_mmu_access);
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* set_exception_vector(0x0b, d_mmu_write);
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*/
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if (cfg_k && tlb_k && usermode) {
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D(printf("tlb: kernel protected %x lo=%x pc=%x\n",
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@ -243,13 +239,15 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
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res->prot = 0;
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if (match) {
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res->prot |= PAGE_READ;
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if (tlb_w)
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if (tlb_w) {
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res->prot |= PAGE_WRITE;
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if (mmu == 0 && (cfg_x || tlb_x))
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}
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if (mmu == 0 && (cfg_x || tlb_x)) {
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res->prot |= PAGE_EXEC;
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}
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else
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} else {
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D(dump_tlb(env, mmu));
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}
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} else {
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/* If refill, provide a randomized set. */
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set = env->mmu_rand_lfsr & 3;
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@ -301,8 +299,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
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pid &= 0xff;
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for (mmu = 0; mmu < 2; mmu++) {
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for (set = 0; set < 4; set++)
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{
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for (set = 0; set < 4; set++) {
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for (idx = 0; idx < 16; idx++) {
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lo = env->tlbsets[mmu][set][idx].lo;
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hi = env->tlbsets[mmu][set][idx].hi;
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@ -314,8 +311,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
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if (tlb_v && !tlb_g && (tlb_pid == pid)) {
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vaddr = tlb_vpn << TARGET_PAGE_BITS;
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D_LOG("flush pid=%x vaddr=%x\n",
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pid, vaddr);
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D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr);
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tlb_flush_page(CPU(cpu), vaddr);
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}
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}
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@ -344,8 +340,7 @@ int cris_mmu_translate(struct cris_mmu_result *res,
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}
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seg = vaddr >> 28;
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if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
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{
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if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) {
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uint32_t base;
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miss = 0;
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