microblaze: Trap on divizions by zero.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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@ -167,7 +167,12 @@ static inline int div_prepare(uint32_t a, uint32_t b)
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{
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if (b == 0) {
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env->sregs[SR_MSR] |= MSR_DZ;
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/* FIXME: Raise the div by zero exception. */
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if ((env->sregs[SR_MSR] & MSR_EE)
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&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
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env->sregs[SR_ESR] = ESR_EC_DIVZERO;
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helper_raise_exception(EXCP_HW_EXCP);
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}
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return 0;
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}
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env->sregs[SR_MSR] &= ~MSR_DZ;
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@ -616,7 +616,6 @@ static void dec_div(DisasContext *dc)
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t_gen_raise_exception(dc, EXCP_HW_EXCP);
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}
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/* FIXME: support div by zero exceptions. */
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if (u)
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gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
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else
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