OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

Split piix4 support from piix_pci.c 

Now mips_malta uses piix4 and pc's use piix_pci definitions

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Juan Quintela 2009-08-28 15:28:13 +02:00 committed by Anthony Liguori
parent a4bf1f3e17
commit 823e675a07
4 changed files with 130 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile.target
View File

@ -214,7 +214,7 @@ obj-mips-y += mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o rc403
obj-mips-y += g364fb.o jazz_led.o dp8393x.o
obj-mips-y += ide/core.o ide/isa.o ide/pci.o
obj-mips-y += gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
obj-mips-y += piix_pci.o parallel.o cirrus_vga.o isa-bus.o pcspk.o $(sound-obj-y)
obj-mips-y += piix4.o parallel.o cirrus_vga.o isa-bus.o pcspk.o $(sound-obj-y)
obj-mips-y += mipsnet.o
obj-mips-y += pflash_cfi01.o
obj-mips-y += vmware_vga.o

1
hw/pc.h
View File

@ -122,6 +122,7 @@ void i440fx_set_smm(PCIDevice *d, int val);
int piix3_init(PCIBus *bus, int devfn);
void i440fx_init_memory_mappings(PCIDevice *d);
/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, int devfn);

128
hw/piix4.c Normal file
View File

@ -0,0 +1,128 @@
/*
* QEMU PIIX4 PCI Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "isa.h"
#include "sysbus.h"
PCIDevice *piix4_dev;
static void piix4_reset(void *opaque)
{
PCIDevice *d = opaque;
uint8_t *pci_conf = d->config;
pci_conf[0x04] = 0x07; // master, memory and I/O
pci_conf[0x05] = 0x00;
pci_conf[0x06] = 0x00;
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
pci_conf[0x4c] = 0x4d;
pci_conf[0x4e] = 0x03;
pci_conf[0x4f] = 0x00;
pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
pci_conf[0x69] = 0x02;
pci_conf[0x70] = 0x80;
pci_conf[0x76] = 0x0c;
pci_conf[0x77] = 0x0c;
pci_conf[0x78] = 0x02;
pci_conf[0x79] = 0x00;
pci_conf[0x80] = 0x00;
pci_conf[0x82] = 0x00;
pci_conf[0xa0] = 0x08;
pci_conf[0xa2] = 0x00;
pci_conf[0xa3] = 0x00;
pci_conf[0xa4] = 0x00;
pci_conf[0xa5] = 0x00;
pci_conf[0xa6] = 0x00;
pci_conf[0xa7] = 0x00;
pci_conf[0xa8] = 0x0f;
pci_conf[0xaa] = 0x00;
pci_conf[0xab] = 0x00;
pci_conf[0xac] = 0x00;
pci_conf[0xae] = 0x00;
}
static void piix_save(QEMUFile* f, void *opaque)
{
PCIDevice *d = opaque;
pci_device_save(d, f);
}
static int piix_load(QEMUFile* f, void *opaque, int version_id)
{
PCIDevice *d = opaque;
if (version_id != 2)
return -EINVAL;
return pci_device_load(d, f);
}
static int piix4_initfn(PCIDevice *d)
{
uint8_t *pci_conf;
register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
pci_conf = d->config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
pci_conf[PCI_HEADER_TYPE] =
PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
piix4_dev = d;
piix4_reset(d);
qemu_register_reset(piix4_reset, d);
return 0;
}
int piix4_init(PCIBus *bus, int devfn)
{
PCIDevice *d;
d = pci_create_simple(bus, devfn, "PIIX4");
return d->devfn;
}
static PCIDeviceInfo piix4_info[] = {
{
.qdev.name = "PIIX4",
.qdev.desc = "ISA bridge",
.qdev.size = sizeof(PCIDevice),
.qdev.no_user = 1,
.init = piix4_initfn,
},{
/* end of list */
}
};
static void piix4_register(void)
{
pci_qdev_register_many(piix4_info);
}
device_init(piix4_register);

72
hw/piix_pci.c
View File

@ -224,7 +224,6 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
/* PIIX3 PCI to ISA bridge */
static PCIDevice *piix3_dev;
PCIDevice *piix4_dev;
static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
{
@ -287,44 +286,6 @@ static void piix3_reset(void *opaque)
memset(pci_irq_levels, 0, sizeof(pci_irq_levels));
}
static void piix4_reset(void *opaque)
{
PCIDevice *d = opaque;
uint8_t *pci_conf = d->config;
pci_conf[0x04] = 0x07; // master, memory and I/O
pci_conf[0x05] = 0x00;
pci_conf[0x06] = 0x00;
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
pci_conf[0x4c] = 0x4d;
pci_conf[0x4e] = 0x03;
pci_conf[0x4f] = 0x00;
pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
pci_conf[0x69] = 0x02;
pci_conf[0x70] = 0x80;
pci_conf[0x76] = 0x0c;
pci_conf[0x77] = 0x0c;
pci_conf[0x78] = 0x02;
pci_conf[0x79] = 0x00;
pci_conf[0x80] = 0x00;
pci_conf[0x82] = 0x00;
pci_conf[0xa0] = 0x08;
pci_conf[0xa2] = 0x00;
pci_conf[0xa3] = 0x00;
pci_conf[0xa4] = 0x00;
pci_conf[0xa5] = 0x00;
pci_conf[0xa6] = 0x00;
pci_conf[0xa7] = 0x00;
pci_conf[0xa8] = 0x0f;
pci_conf[0xaa] = 0x00;
pci_conf[0xab] = 0x00;
pci_conf[0xac] = 0x00;
pci_conf[0xae] = 0x00;
}
static void piix_save(QEMUFile* f, void *opaque)
{
PCIDevice *d = opaque;
@ -359,25 +320,6 @@ static int piix3_initfn(PCIDevice *d)
return 0;
}
static int piix4_initfn(PCIDevice *d)
{
uint8_t *pci_conf;
register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
pci_conf = d->config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
pci_conf[PCI_HEADER_TYPE] =
PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
piix4_dev = d;
piix4_reset(d);
qemu_register_reset(piix4_reset, d);
return 0;
}
int piix3_init(PCIBus *bus, int devfn)
{
PCIDevice *d;
@ -386,14 +328,6 @@ int piix3_init(PCIBus *bus, int devfn)
return d->devfn;
}
int piix4_init(PCIBus *bus, int devfn)
{
PCIDevice *d;
d = pci_create_simple(bus, devfn, "PIIX4");
return d->devfn;
}
static PCIDeviceInfo i440fx_info[] = {
{
.qdev.name = "i440FX",
@ -408,12 +342,6 @@ static PCIDeviceInfo i440fx_info[] = {
.qdev.size = sizeof(PCIDevice),
.qdev.no_user = 1,
.init = piix3_initfn,
},{
.qdev.name = "PIIX4",
.qdev.desc = "ISA bridge",
.qdev.size = sizeof(PCIDevice),
.qdev.no_user = 1,
.init = piix4_initfn,
},{
/* end of list */
}