openpic: combine openpic and mpic reset functions
The openpic and mpic reset handlers are almost identical. Combine them and extract the differences into state variables. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
c38c0b8ad0
commit
825463b384
103
hw/openpic.c
103
hw/openpic.c
@ -53,7 +53,6 @@
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#define MAX_IPI 4
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#define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
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#define VID 0x03 /* MPIC version ID */
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#define VENI 0x00000000 /* Vendor ID */
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enum {
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IRQ_IPVP = 0,
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@ -125,6 +124,14 @@ enum {
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#define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */
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#define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */
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#define FREP_NIRQ_SHIFT 16
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#define FREP_NCPU_SHIFT 8
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#define FREP_VID_SHIFT 0
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#define VID_REVISION_1_2 2
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#define VENI_GENERIC 0x00000000 /* Generic Vendor ID */
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enum mpic_ide_bits {
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IDR_EP = 31,
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IDR_CI0 = 30,
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@ -208,6 +215,13 @@ typedef struct openpic_t {
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/* Behavior control */
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uint32_t flags;
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uint32_t nb_irqs;
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uint32_t vid;
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uint32_t veni; /* Vendor identification register */
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uint32_t spve_mask;
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uint32_t tifr_reset;
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uint32_t ipvp_reset;
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uint32_t ide_reset;
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/* Sub-regions */
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MemoryRegion sub_io_mem[7];
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@ -215,8 +229,6 @@ typedef struct openpic_t {
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/* Global registers */
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uint32_t frep; /* Feature reporting register */
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uint32_t glbc; /* Global configuration register */
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uint32_t micr; /* MPIC interrupt configuration register */
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uint32_t veni; /* Vendor identification register */
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uint32_t pint; /* Processor initialization register */
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uint32_t spve; /* Spurious vector register */
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uint32_t tifr; /* Timer frequency reporting register */
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@ -235,7 +247,6 @@ typedef struct openpic_t {
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int max_irq;
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int irq_ipi0;
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int irq_tim0;
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void (*reset) (void *);
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} openpic_t;
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static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
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@ -412,17 +423,17 @@ static void openpic_reset (void *opaque)
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opp->glbc = 0x80000000;
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/* Initialise controller registers */
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opp->frep = ((OPENPIC_EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID;
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opp->veni = VENI;
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opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) |
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((opp->nb_cpus -1) << FREP_NCPU_SHIFT) |
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(opp->vid << FREP_VID_SHIFT);
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opp->pint = 0x00000000;
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opp->spve = 0x000000FF;
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opp->tifr = 0x003F7A00;
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/* ? */
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opp->micr = 0x00000000;
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opp->spve = -1 & opp->spve_mask;
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opp->tifr = opp->tifr_reset;
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/* Initialise IRQ sources */
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for (i = 0; i < opp->max_irq; i++) {
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opp->src[i].ipvp = 0xA0000000;
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opp->src[i].ide = 0x00000000;
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opp->src[i].ipvp = opp->ipvp_reset;
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opp->src[i].ide = opp->ide_reset;
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}
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/* Initialise IRQ destinations */
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for (i = 0; i < MAX_CPU; i++) {
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@ -499,9 +510,9 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
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case 0x1000: /* FREP */
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break;
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case 0x1020: /* GLBC */
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if (val & 0x80000000 && opp->reset)
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opp->reset(opp);
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opp->glbc = val & ~0x80000000;
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if (val & 0x80000000) {
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openpic_reset(opp);
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}
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break;
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case 0x1080: /* VENI */
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break;
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@ -530,7 +541,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
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}
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break;
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case 0x10E0: /* SPVE */
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opp->spve = val & 0x000000FF;
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opp->spve = val & opp->spve_mask;
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break;
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default:
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break;
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@ -912,9 +923,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
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openpic_t *opp = (openpic_t *)opaque;
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unsigned int i;
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qemu_put_be32s(f, &opp->frep);
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qemu_put_be32s(f, &opp->glbc);
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qemu_put_be32s(f, &opp->micr);
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qemu_put_be32s(f, &opp->veni);
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qemu_put_be32s(f, &opp->pint);
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qemu_put_be32s(f, &opp->spve);
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@ -964,9 +973,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
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if (version_id != 1)
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return -EINVAL;
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qemu_get_be32s(f, &opp->frep);
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qemu_get_be32s(f, &opp->glbc);
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qemu_get_be32s(f, &opp->micr);
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qemu_get_be32s(f, &opp->veni);
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qemu_get_be32s(f, &opp->pint);
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qemu_get_be32s(f, &opp->spve);
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@ -1043,6 +1050,11 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
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// isu_base &= 0xFFFC0000;
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opp->nb_cpus = nb_cpus;
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opp->nb_irqs = OPENPIC_EXT_IRQ;
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opp->vid = VID;
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opp->veni = VENI_GENERIC;
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opp->spve_mask = 0xFF;
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opp->tifr_reset = 0x003F7A00;
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opp->max_irq = OPENPIC_MAX_IRQ;
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opp->irq_ipi0 = OPENPIC_IRQ_IPI0;
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opp->irq_tim0 = OPENPIC_IRQ_TIM0;
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@ -1068,51 +1080,12 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
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openpic_save, openpic_load, opp);
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qemu_register_reset(openpic_reset, opp);
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opp->reset = openpic_reset;
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if (pmem)
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*pmem = &opp->mem;
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return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
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}
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static void mpic_reset (void *opaque)
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{
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openpic_t *mpp = (openpic_t *)opaque;
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int i;
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mpp->glbc = 0x80000000;
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/* Initialise controller registers */
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mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8);
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mpp->veni = VENI;
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mpp->pint = 0x00000000;
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mpp->spve = 0x0000FFFF;
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/* Initialise IRQ sources */
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for (i = 0; i < mpp->max_irq; i++) {
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mpp->src[i].ipvp = 0x80800000;
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mpp->src[i].ide = 0x00000001;
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}
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/* Set IDE for IPIs to 0 so we don't get spurious interrupts */
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for (i = mpp->irq_ipi0; i < (mpp->irq_ipi0 + MAX_IPI); i++) {
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mpp->src[i].ide = 0;
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}
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/* Initialise IRQ destinations */
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for (i = 0; i < MAX_CPU; i++) {
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mpp->dst[i].pctp = 0x0000000F;
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memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t));
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mpp->dst[i].raised.next = -1;
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memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
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mpp->dst[i].servicing.next = -1;
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}
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/* Initialise timers */
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for (i = 0; i < MAX_TMR; i++) {
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mpp->timers[i].ticc = 0x00000000;
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mpp->timers[i].tibc = 0x80000000;
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}
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/* Go out of RESET state */
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mpp->glbc = 0x00000000;
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}
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static const MemoryRegionOps mpic_glb_ops = {
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.write = openpic_gbl_write,
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.read = openpic_gbl_read,
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@ -1185,6 +1158,15 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
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}
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mpp->nb_cpus = nb_cpus;
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/* 12 external sources, 48 internal sources , 4 timer sources,
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4 IPI sources, 4 messaging sources, and 8 Shared MSI sources */
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mpp->nb_irqs = 80;
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mpp->vid = VID_REVISION_1_2;
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mpp->veni = VENI_GENERIC;
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mpp->spve_mask = 0xFFFF;
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mpp->tifr_reset = 0x00000000;
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mpp->ipvp_reset = 0x80000000;
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mpp->ide_reset = 0x00000001;
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mpp->max_irq = MPIC_MAX_IRQ;
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mpp->irq_ipi0 = MPIC_IPI_IRQ;
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mpp->irq_tim0 = MPIC_TMR_IRQ;
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@ -1195,10 +1177,9 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
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/* Enable critical interrupt support */
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mpp->flags |= OPENPIC_FLAG_IDE_CRIT;
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mpp->reset = mpic_reset;
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register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
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qemu_register_reset(mpic_reset, mpp);
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qemu_register_reset(openpic_reset, mpp);
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return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
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}
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