Preliminary Sparc TCG target
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3995 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
b25deda7ca
commit
8289b27975
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@ -177,6 +177,9 @@ LIBOBJS=exec.o kqemu.o translate-all.o cpu-exec.o\
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# TCG code generator
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LIBOBJS+= tcg/tcg.o tcg/tcg-dyngen.o tcg/tcg-runtime.o
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CPPFLAGS+=-I$(SRC_PATH)/tcg -I$(SRC_PATH)/tcg/$(ARCH)
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ifeq ($(ARCH),sparc64)
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CPPFLAGS+=-I$(SRC_PATH)/tcg/sparc
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endif
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ifdef CONFIG_SOFTFLOAT
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LIBOBJS+=fpu/softfloat.o
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else
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2
dyngen.c
2
dyngen.c
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@ -1615,12 +1615,14 @@ void gen_code(const char *name, host_ulong offset, host_ulong size,
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error("No save at the beginning of %s", name);
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}
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#if 0
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/* Skip a preceeding nop, if present. */
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if (p > p_start) {
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skip_insn = get32((uint32_t *)(p - 0x4));
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if (skip_insn == 0x01000000)
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p -= 4;
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}
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#endif
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copy_size = p - p_start;
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}
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@ -0,0 +1,612 @@
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"%g0",
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"%g1",
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"%g2",
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"%g3",
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"%g4",
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"%g5",
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"%g6",
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"%g7",
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"%o0",
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"%o1",
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"%o2",
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"%o3",
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"%o4",
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"%o5",
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"%o6",
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"%o7",
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"%l0",
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"%l1",
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"%l2",
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"%l3",
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"%l4",
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"%l5",
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"%l6",
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"%l7",
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"%i0",
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"%i1",
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"%i2",
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"%i3",
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"%i4",
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"%i5",
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"%i6",
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"%i7",
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};
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static const int tcg_target_reg_alloc_order[TCG_TARGET_NB_REGS] = {
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TCG_REG_L0,
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TCG_REG_L1,
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TCG_REG_L2,
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TCG_REG_L3,
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TCG_REG_L4,
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TCG_REG_L5,
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TCG_REG_L6,
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TCG_REG_L7,
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TCG_REG_I0,
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TCG_REG_I1,
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TCG_REG_I2,
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TCG_REG_I3,
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TCG_REG_I4,
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TCG_REG_I5,
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};
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static const int tcg_target_call_iarg_regs[6] = {
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TCG_REG_O0,
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TCG_REG_O1,
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TCG_REG_O2,
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TCG_REG_O3,
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TCG_REG_O4,
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TCG_REG_O5,
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};
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static const int tcg_target_call_oarg_regs[2] = {
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TCG_REG_O0,
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TCG_REG_O1,
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};
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static void patch_reloc(uint8_t *code_ptr, int type,
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tcg_target_long value)
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{
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switch (type) {
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case R_SPARC_32:
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if (value != (uint32_t)value)
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tcg_abort();
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*(uint32_t *)code_ptr = value;
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break;
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default:
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tcg_abort();
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}
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}
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags)
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{
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return 6;
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}
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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const char *ct_str;
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ct_str = *pct_str;
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switch (ct_str[0]) {
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case 'r':
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case 'L': /* qemu_ld/st constraint */
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
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break;
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case 'I':
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ct->ct |= TCG_CT_CONST_S11;
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break;
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case 'J':
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ct->ct |= TCG_CT_CONST_S13;
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break;
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default:
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return -1;
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}
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ct_str++;
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*pct_str = ct_str;
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return 0;
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}
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#define ABS(x) ((x) < 0? -(x) : (x))
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val,
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const TCGArgConstraint *arg_ct)
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{
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int ct;
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ct = arg_ct->ct;
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if (ct & TCG_CT_CONST)
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return 1;
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else if ((ct & TCG_CT_CONST_S11) && ABS(val) == (ABS(val) & 0x3ff))
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return 1;
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else if ((ct & TCG_CT_CONST_S13) && ABS(val) == (ABS(val) & 0xfff))
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return 1;
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else
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return 0;
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}
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#define INSN_OP(x) ((x) << 30)
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#define INSN_OP2(x) ((x) << 22)
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#define INSN_OP3(x) ((x) << 19)
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#define INSN_OPF(x) ((x) << 5)
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#define INSN_RD(x) ((x) << 25)
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#define INSN_RS1(x) ((x) << 14)
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#define INSN_RS2(x) (x)
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#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
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#define INSN_COND(x, a) (((x) << 25) | ((a) << 29)
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#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
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#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
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#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
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#define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03))
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#define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x08))
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#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
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#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
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#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
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#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
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#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
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#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
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#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
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#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
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#define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25))
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#define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26))
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#define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27))
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#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
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#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
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#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
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#define WRY (INSN_OP(2) | INSN_OP3(0x30))
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#define JMPL (INSN_OP(2) | INSN_OP3(0x38))
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#define SAVE (INSN_OP(2) | INSN_OP3(0x3c))
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#define RESTORE (INSN_OP(2) | INSN_OP3(0x3d))
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#define SETHI (INSN_OP(0) | INSN_OP2(0x4))
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#define CALL INSN_OP(1)
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#define LDUB (INSN_OP(3) | INSN_OP3(0x01))
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#define LDSB (INSN_OP(3) | INSN_OP3(0x09))
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#define LDUH (INSN_OP(3) | INSN_OP3(0x02))
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#define LDSH (INSN_OP(3) | INSN_OP3(0x0a))
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#define LDUW (INSN_OP(3) | INSN_OP3(0x00))
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#define LDSW (INSN_OP(3) | INSN_OP3(0x08))
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#define LDX (INSN_OP(3) | INSN_OP3(0x0b))
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#define STB (INSN_OP(3) | INSN_OP3(0x05))
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#define STH (INSN_OP(3) | INSN_OP3(0x06))
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#define STW (INSN_OP(3) | INSN_OP3(0x04))
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#define STX (INSN_OP(3) | INSN_OP3(0x0e))
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static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
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{
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tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(arg) |
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INSN_RS2(TCG_REG_G0));
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}
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static inline void tcg_out_movi(TCGContext *s, TCGType type,
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int ret, tcg_target_long arg)
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{
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if (arg == (arg & 0xfff))
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tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS2(TCG_REG_G0) |
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INSN_IMM13(arg));
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else {
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tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
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if (arg & 0x3ff)
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tcg_out32(s, ARITH_OR | INSN_RD(ret) | INSN_RS1(ret) |
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INSN_IMM13(arg & 0x3ff));
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}
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}
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static inline void tcg_out_ld_raw(TCGContext *s, int ret,
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tcg_target_long arg)
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{
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tcg_out32(s, SETHI | INSN_RD(ret) | (((uint32_t)arg & 0xfffffc00) >> 10));
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tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
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INSN_IMM13(arg & 0x3ff));
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}
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static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
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{
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if (offset == (offset & 0xfff))
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tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
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INSN_IMM13(offset));
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else
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fprintf(stderr, "unimplemented %s with offset %d\n", __func__, offset);
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}
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static inline void tcg_out_ld(TCGContext *s, int ret,
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int arg1, tcg_target_long arg2)
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{
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fprintf(stderr, "unimplemented %s\n", __func__);
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}
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static inline void tcg_out_st(TCGContext *s, int arg,
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int arg1, tcg_target_long arg2)
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{
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fprintf(stderr, "unimplemented %s\n", __func__);
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}
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static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
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int op)
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{
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tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
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INSN_RS2(rs2));
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}
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static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, int offset,
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int op)
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{
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tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
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INSN_IMM13(offset));
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}
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static inline void tcg_out_sety(TCGContext *s, tcg_target_long val)
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{
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if (val == 0 || val == -1)
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tcg_out32(s, WRY | INSN_IMM13(val));
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else
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fprintf(stderr, "unimplemented sety %ld\n", (long)val);
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}
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static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
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{
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if (val != 0) {
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if (val == (val & 0xfff))
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tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
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else
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fprintf(stderr, "unimplemented addi %ld\n", (long)val);
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}
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}
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static inline void tcg_out_nop(TCGContext *s)
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{
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tcg_out32(s, SETHI | INSN_RD(TCG_REG_G0) | 0);
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}
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static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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const int *const_args)
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{
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int c;
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switch (opc) {
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case INDEX_op_exit_tb:
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tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_O0, args[0]);
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_O7) |
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INSN_IMM13(8));
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tcg_out_nop(s);
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break;
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case INDEX_op_goto_tb:
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if (s->tb_jmp_offset) {
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/* direct jump method */
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tcg_out32(s, CALL | 0);
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s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
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tcg_out_nop(s);
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} else {
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/* indirect jump method */
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tcg_out_ld_raw(s, TCG_REG_O7, (tcg_target_long)(s->tb_next + args[0]));
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_O7) |
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INSN_RD(TCG_REG_G0));
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tcg_out_nop(s);
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}
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s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
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break;
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case INDEX_op_call:
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if (const_args[0]) {
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tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
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- (tcg_target_ulong)s->code_ptr) >> 2)
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& 0x3fffffff));
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tcg_out_nop(s);
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} else {
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tcg_out_ld_raw(s, TCG_REG_O7, (tcg_target_long)(s->tb_next + args[0]));
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_O7) |
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INSN_RD(TCG_REG_G0));
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tcg_out_nop(s);
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}
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break;
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case INDEX_op_jmp:
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fprintf(stderr, "unimplemented jmp\n");
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break;
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case INDEX_op_br:
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fprintf(stderr, "unimplemented br\n");
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break;
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case INDEX_op_movi_i32:
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tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
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break;
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#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
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#define OP_32_64(x) \
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glue(glue(case INDEX_op_, x), _i32:) \
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glue(glue(case INDEX_op_, x), _i64:)
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#else
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#define OP_32_64(x) \
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glue(glue(case INDEX_op_, x), _i32:)
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#endif
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OP_32_64(ld8u);
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tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
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break;
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OP_32_64(ld8s);
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tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
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break;
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OP_32_64(ld16u);
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tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
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break;
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OP_32_64(ld16s);
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tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
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break;
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case INDEX_op_ld_i32:
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#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
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case INDEX_op_ld_i32u_i64:
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#endif
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tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
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break;
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OP_32_64(st8);
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tcg_out_ldst(s, args[0], args[1], args[2], STB);
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break;
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OP_32_64(st16);
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tcg_out_ldst(s, args[0], args[1], args[2], STH);
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break;
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case INDEX_op_st_i32:
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#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
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case INDEX_op_st_i32_i64:
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#endif
|
||||
tcg_out_ldst(s, args[0], args[1], args[2], STW);
|
||||
break;
|
||||
OP_32_64(sub);
|
||||
c = ARITH_SUB;
|
||||
goto gen_arith32;
|
||||
OP_32_64(and);
|
||||
c = ARITH_AND;
|
||||
goto gen_arith32;
|
||||
OP_32_64(or);
|
||||
c = ARITH_OR;
|
||||
goto gen_arith32;
|
||||
OP_32_64(xor);
|
||||
c = ARITH_XOR;
|
||||
goto gen_arith32;
|
||||
case INDEX_op_shl_i32:
|
||||
c = SHIFT_SLL;
|
||||
goto gen_arith32;
|
||||
case INDEX_op_shr_i32:
|
||||
c = SHIFT_SRL;
|
||||
goto gen_arith32;
|
||||
case INDEX_op_sar_i32:
|
||||
c = SHIFT_SRA;
|
||||
goto gen_arith32;
|
||||
case INDEX_op_mul_i32:
|
||||
c = ARITH_UMUL;
|
||||
goto gen_arith32;
|
||||
OP_32_64(add);
|
||||
c = ARITH_ADD;
|
||||
gen_arith32:
|
||||
if (const_args[2]) {
|
||||
tcg_out_arithi(s, args[0], args[1], args[2], c);
|
||||
} else {
|
||||
tcg_out_arith(s, args[0], args[1], args[2], c);
|
||||
}
|
||||
break;
|
||||
|
||||
case INDEX_op_div2_i32:
|
||||
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
||||
c = ARITH_SDIVX;
|
||||
goto gen_arith32;
|
||||
#else
|
||||
tcg_out_sety(s, 0);
|
||||
c = ARITH_SDIV;
|
||||
goto gen_arith32;
|
||||
#endif
|
||||
case INDEX_op_divu2_i32:
|
||||
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
||||
c = ARITH_UDIVX;
|
||||
goto gen_arith32;
|
||||
#else
|
||||
tcg_out_sety(s, 0);
|
||||
c = ARITH_UDIV;
|
||||
goto gen_arith32;
|
||||
#endif
|
||||
|
||||
case INDEX_op_brcond_i32:
|
||||
fprintf(stderr, "unimplemented brcond\n");
|
||||
break;
|
||||
|
||||
case INDEX_op_qemu_ld8u:
|
||||
fprintf(stderr, "unimplemented qld\n");
|
||||
break;
|
||||
case INDEX_op_qemu_ld8s:
|
||||
fprintf(stderr, "unimplemented qld\n");
|
||||
break;
|
||||
case INDEX_op_qemu_ld16u:
|
||||
fprintf(stderr, "unimplemented qld\n");
|
||||
break;
|
||||
case INDEX_op_qemu_ld16s:
|
||||
fprintf(stderr, "unimplemented qld\n");
|
||||
break;
|
||||
case INDEX_op_qemu_ld32u:
|
||||
fprintf(stderr, "unimplemented qld\n");
|
||||
break;
|
||||
case INDEX_op_qemu_ld32s:
|
||||
fprintf(stderr, "unimplemented qld\n");
|
||||
break;
|
||||
case INDEX_op_qemu_st8:
|
||||
fprintf(stderr, "unimplemented qst\n");
|
||||
break;
|
||||
case INDEX_op_qemu_st16:
|
||||
fprintf(stderr, "unimplemented qst\n");
|
||||
break;
|
||||
case INDEX_op_qemu_st32:
|
||||
fprintf(stderr, "unimplemented qst\n");
|
||||
break;
|
||||
|
||||
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
||||
case INDEX_op_movi_i64:
|
||||
tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
|
||||
break;
|
||||
case INDEX_op_ld_i64:
|
||||
tcg_out_ldst(s, args[0], args[1], args[2], LDX);
|
||||
break;
|
||||
case INDEX_op_st_i64:
|
||||
tcg_out_ldst(s, args[0], args[1], args[2], STX);
|
||||
break;
|
||||
case INDEX_op_shl_i64:
|
||||
c = SHIFT_SLLX;
|
||||
goto gen_arith32;
|
||||
case INDEX_op_shr_i64:
|
||||
c = SHIFT_SRLX;
|
||||
goto gen_arith32;
|
||||
case INDEX_op_sar_i64:
|
||||
c = SHIFT_SRAX;
|
||||
goto gen_arith32;
|
||||
case INDEX_op_mul_i64:
|
||||
c = ARITH_MULX;
|
||||
goto gen_arith32;
|
||||
case INDEX_op_div2_i64:
|
||||
c = ARITH_DIVX;
|
||||
goto gen_arith32;
|
||||
case INDEX_op_divu2_i64:
|
||||
c = ARITH_UDIVX;
|
||||
goto gen_arith32;
|
||||
|
||||
case INDEX_op_brcond_i64:
|
||||
fprintf(stderr, "unimplemented brcond\n");
|
||||
break;
|
||||
case INDEX_op_qemu_ld64:
|
||||
fprintf(stderr, "unimplemented qld\n");
|
||||
break;
|
||||
case INDEX_op_qemu_st64:
|
||||
fprintf(stderr, "unimplemented qst\n");
|
||||
break;
|
||||
|
||||
#endif
|
||||
default:
|
||||
fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
||||
tcg_abort();
|
||||
}
|
||||
}
|
||||
|
||||
static const TCGTargetOpDef sparc_op_defs[] = {
|
||||
{ INDEX_op_exit_tb, { } },
|
||||
{ INDEX_op_goto_tb, { } },
|
||||
{ INDEX_op_call, { "ri" } },
|
||||
{ INDEX_op_jmp, { "ri" } },
|
||||
{ INDEX_op_br, { } },
|
||||
|
||||
{ INDEX_op_mov_i32, { "r", "r" } },
|
||||
{ INDEX_op_movi_i32, { "r" } },
|
||||
{ INDEX_op_ld8u_i32, { "r", "r" } },
|
||||
{ INDEX_op_ld8s_i32, { "r", "r" } },
|
||||
{ INDEX_op_ld16u_i32, { "r", "r" } },
|
||||
{ INDEX_op_ld16s_i32, { "r", "r" } },
|
||||
{ INDEX_op_ld_i32, { "r", "r" } },
|
||||
{ INDEX_op_st8_i32, { "r", "r" } },
|
||||
{ INDEX_op_st16_i32, { "r", "r" } },
|
||||
{ INDEX_op_st_i32, { "r", "r" } },
|
||||
|
||||
{ INDEX_op_add_i32, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_mul_i32, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } },
|
||||
{ INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } },
|
||||
{ INDEX_op_sub_i32, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_and_i32, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_or_i32, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_xor_i32, { "r", "0", "rJ" } },
|
||||
|
||||
{ INDEX_op_shl_i32, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_shr_i32, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_sar_i32, { "r", "0", "rJ" } },
|
||||
|
||||
{ INDEX_op_brcond_i32, { "r", "ri" } },
|
||||
|
||||
{ INDEX_op_qemu_ld8u, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld8s, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld16u, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld16s, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld32u, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld32s, { "r", "L" } },
|
||||
|
||||
{ INDEX_op_qemu_st8, { "L", "L" } },
|
||||
{ INDEX_op_qemu_st16, { "L", "L" } },
|
||||
{ INDEX_op_qemu_st32, { "L", "L" } },
|
||||
|
||||
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
||||
{ INDEX_op_mov_i64, { "r", "r" } },
|
||||
{ INDEX_op_movi_i64, { "r" } },
|
||||
{ INDEX_op_ld8u_i64, { "r", "r" } },
|
||||
{ INDEX_op_ld8s_i64, { "r", "r" } },
|
||||
{ INDEX_op_ld16u_i64, { "r", "r" } },
|
||||
{ INDEX_op_ld16s_i64, { "r", "r" } },
|
||||
{ INDEX_op_ld32u_i64, { "r", "r" } },
|
||||
{ INDEX_op_ld32s_i64, { "r", "r" } },
|
||||
{ INDEX_op_ld_i64, { "r", "r" } },
|
||||
{ INDEX_op_st8_i64, { "r", "r" } },
|
||||
{ INDEX_op_st16_i64, { "r", "r" } },
|
||||
{ INDEX_op_st32_i64, { "r", "r" } },
|
||||
{ INDEX_op_st_i64, { "r", "r" } },
|
||||
|
||||
{ INDEX_op_add_i64, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_mul_i64, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } },
|
||||
{ INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } },
|
||||
{ INDEX_op_sub_i64, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_and_i64, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_or_i64, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_xor_i64, { "r", "0", "rJ" } },
|
||||
|
||||
{ INDEX_op_shl_i64, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_shr_i64, { "r", "0", "rJ" } },
|
||||
{ INDEX_op_sar_i64, { "r", "0", "rJ" } },
|
||||
|
||||
{ INDEX_op_brcond_i64, { "r", "ri" } },
|
||||
#endif
|
||||
{ -1 },
|
||||
};
|
||||
|
||||
void tcg_target_init(TCGContext *s)
|
||||
{
|
||||
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
|
||||
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
||||
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
|
||||
#endif
|
||||
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
||||
(1 << TCG_REG_O0) |
|
||||
(1 << TCG_REG_O1) |
|
||||
(1 << TCG_REG_O2) |
|
||||
(1 << TCG_REG_O3) |
|
||||
(1 << TCG_REG_O4) |
|
||||
(1 << TCG_REG_O5) |
|
||||
(1 << TCG_REG_O6) |
|
||||
(1 << TCG_REG_O7));
|
||||
|
||||
tcg_regset_clear(s->reserved_regs);
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
|
||||
tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
|
||||
tcg_add_target_add_op_defs(sparc_op_defs);
|
||||
}
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* Tiny Code Generator for QEMU
|
||||
*
|
||||
* Copyright (c) 2008 Fabrice Bellard
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#define TCG_TARGET_SPARC 1
|
||||
|
||||
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
||||
#define TCG_TARGET_REG_BITS 64
|
||||
#else
|
||||
#define TCG_TARGET_REG_BITS 32
|
||||
#endif
|
||||
|
||||
#define TCG_TARGET_WORDS_BIGENDIAN
|
||||
|
||||
#define TCG_TARGET_NB_REGS 32
|
||||
|
||||
enum {
|
||||
TCG_REG_G0 = 0,
|
||||
TCG_REG_G1,
|
||||
TCG_REG_G2,
|
||||
TCG_REG_G3,
|
||||
TCG_REG_G4,
|
||||
TCG_REG_G5,
|
||||
TCG_REG_G6,
|
||||
TCG_REG_G7,
|
||||
TCG_REG_O0,
|
||||
TCG_REG_O1,
|
||||
TCG_REG_O2,
|
||||
TCG_REG_O3,
|
||||
TCG_REG_O4,
|
||||
TCG_REG_O5,
|
||||
TCG_REG_O6,
|
||||
TCG_REG_O7,
|
||||
TCG_REG_L0,
|
||||
TCG_REG_L1,
|
||||
TCG_REG_L2,
|
||||
TCG_REG_L3,
|
||||
TCG_REG_L4,
|
||||
TCG_REG_L5,
|
||||
TCG_REG_L6,
|
||||
TCG_REG_L7,
|
||||
TCG_REG_I0,
|
||||
TCG_REG_I1,
|
||||
TCG_REG_I2,
|
||||
TCG_REG_I3,
|
||||
TCG_REG_I4,
|
||||
TCG_REG_I5,
|
||||
TCG_REG_I6,
|
||||
TCG_REG_I7,
|
||||
};
|
||||
|
||||
#define TCG_CT_CONST_S11 0x100
|
||||
#define TCG_CT_CONST_S13 0x200
|
||||
|
||||
/* used for function call generation */
|
||||
#define TCG_REG_CALL_STACK TCG_REG_O6
|
||||
#define TCG_TARGET_STACK_ALIGN 16
|
||||
|
||||
/* optional instructions */
|
||||
//#define TCG_TARGET_HAS_bswap_i32
|
||||
//#define TCG_TARGET_HAS_bswap_i64
|
||||
|
||||
/* Note: must be synced with dyngen-exec.h */
|
||||
#ifdef HOST_SOLARIS
|
||||
#define TCG_AREG0 TCG_REG_G2
|
||||
#define TCG_AREG1 TCG_REG_G3
|
||||
#define TCG_AREG2 TCG_REG_G4
|
||||
#define TCG_AREG3 TCG_REG_G5
|
||||
#define TCG_AREG4 TCG_REG_G6
|
||||
#elif defined(__sparc_v9__)
|
||||
#define TCG_AREG0 TCG_REG_G1
|
||||
#define TCG_AREG1 TCG_REG_G4
|
||||
#define TCG_AREG2 TCG_REG_G5
|
||||
#define TCG_AREG3 TCG_REG_G7
|
||||
#else
|
||||
#define TCG_AREG0 TCG_REG_G6
|
||||
#define TCG_AREG1 TCG_REG_G1
|
||||
#define TCG_AREG2 TCG_REG_G2
|
||||
#define TCG_AREG3 TCG_REG_G3
|
||||
#endif
|
||||
|
||||
static inline void flush_icache_range(unsigned long start, unsigned long stop)
|
||||
{
|
||||
unsigned long p;
|
||||
|
||||
p = start & ~(8UL - 1UL);
|
||||
stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
|
||||
|
||||
for (; p < stop; p += 8)
|
||||
__asm__ __volatile__("flush\t%0" : : "r" (p));
|
||||
}
|
||||
Loading…
Reference in New Issue