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SPARC host fixes, by Ben Taylor. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2503 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-03-19 14:47:40 +00:00
parent ee999a8899
commit 8294eba187
3 changed files with 2 additions and 35 deletions
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8
target-arm/exec.h
View File

@ -17,19 +17,13 @@
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "config.h"
#include "dyngen-exec.h"
#if defined(__sparc__)
struct CPUARMState *env;
uint32_t T0;
uint32_t T1;
uint32_t T2;
#else
register struct CPUARMState *env asm(AREG0);
register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
register uint32_t T2 asm(AREG3);
#endif
/* TODO: Put these in FP regs on targets that have such things. */
/* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */

10
target-mips/exec.h
View File

@ -7,11 +7,7 @@
#include "mips-defs.h"
#include "dyngen-exec.h"
#if defined(__sparc__)
struct CPUMIPSState *env;
#else
register struct CPUMIPSState *env asm(AREG0);
#endif
#if defined (USE_64BITS_REGS)
typedef int64_t host_int_t;
@ -21,11 +17,6 @@ typedef int32_t host_int_t;
typedef uint32_t host_uint_t;
#endif
#if defined(__sparc__)
host_uint_t T0;
host_uint_t T1;
host_uint_t T2;
#else
#if TARGET_LONG_BITS > HOST_LONG_BITS
#define T0 (env->t0)
#define T1 (env->t1)
@ -35,7 +26,6 @@ register host_uint_t T0 asm(AREG1);
register host_uint_t T1 asm(AREG2);
register host_uint_t T2 asm(AREG3);
#endif
#endif
#if defined (USE_HOST_FLOAT_REGS)
#error "implement me."

19
target-sparc/exec.h
View File

@ -1,13 +1,9 @@
#ifndef EXEC_SPARC_H
#define EXEC_SPARC_H 1
#include "dyngen-exec.h"
#include "config.h"
#include "dyngen-exec.h"
#if defined(__sparc__)
struct CPUSPARCState *env;
#else
register struct CPUSPARCState *env asm(AREG0);
#endif
#ifdef TARGET_SPARC64
#define T0 (env->t0)
@ -15,13 +11,8 @@ register struct CPUSPARCState *env asm(AREG0);
#define T2 (env->t2)
#define REGWPTR env->regwptr
#else
#if defined(__sparc__)
register uint32_t T0 asm(AREG3);
register uint32_t T1 asm(AREG2);
#else
register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
#endif
#undef REG_REGWPTR // Broken
#ifdef REG_REGWPTR
@ -33,11 +24,7 @@ register uint32_t *REGWPTR asm(AREG3);
#define reg_REGWPTR
#ifdef AREG4
#if defined(__sparc__)
register uint32_t T2 asm(AREG0);
#else
register uint32_t T2 asm(AREG4);
#endif
#define reg_T2
#else
#define T2 (env->t2)
@ -45,14 +32,10 @@ register uint32_t T2 asm(AREG4);
#else
#define REGWPTR env->regwptr
#if defined(__sparc__)
register uint32_t T2 asm(AREG0);
#else
register uint32_t T2 asm(AREG3);
#endif
#define reg_T2
#endif
#endif
#define FT0 (env->ft0)
#define FT1 (env->ft1)