From 82b641d6261a58d9fba5a6ce786e7d58a8876e25 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 9 Oct 2023 12:34:50 +0200 Subject: [PATCH] target/i386/hvf: Use x86_cpu in simulate_[rdmsr|wrmsr]() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We already have 'x86_cpu = X86_CPU(cpu)'. Use the variable instead of doing another QOM cast with X86_CPU(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Reviewed-by: Zhao Liu Message-Id: <20231009110239.66778-6-philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index ccda568478..af1f205ecf 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -676,7 +676,7 @@ void simulate_rdmsr(struct CPUState *cpu) val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: - val = cpu_get_apic_base(X86_CPU(cpu)->apic_state); + val = cpu_get_apic_base(x86_cpu->apic_state); break; case MSR_IA32_UCODE_REV: val = x86_cpu->ucode_rev; @@ -776,7 +776,7 @@ void simulate_wrmsr(struct CPUState *cpu) case MSR_IA32_TSC: break; case MSR_IA32_APICBASE: - cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); + cpu_set_apic_base(x86_cpu->apic_state, data); break; case MSR_FSBASE: wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data);