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target/ppc: Implement cntlzdm

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Implement the following PowerISA v3.1 instruction:
cntlzdm: Count Leading Zeros Doubleword Under Bit Mask

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211029202424.175401-8-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Luis Pires 2021-10-29 17:23:57 -03:00 committed by David Gibson
parent 49de064889
commit 82be6e02b4
2 changed files with 37 additions and 0 deletions
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1
target/ppc/insn32.decode
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@ -124,6 +124,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X
CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
### Float-Point Load Instructions

36
target/ppc/translate/fixedpoint-impl.c.inc
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@ -413,3 +413,39 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
#endif
return true;
}
#if defined(TARGET_PPC64)
static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
{
TCGv_i64 tmp;
TCGLabel *l1;
tmp = tcg_temp_local_new_i64();
l1 = gen_new_label();
tcg_gen_and_i64(tmp, src, mask);
tcg_gen_clzi_i64(tmp, tmp, 64);
tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
tcg_gen_subfi_i64(tmp, 64, tmp);
tcg_gen_shr_i64(tmp, mask, tmp);
tcg_gen_ctpop_i64(tmp, tmp);
gen_set_label(l1);
tcg_gen_mov_i64(dst, tmp);
}
#endif
static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
#if defined(TARGET_PPC64)
do_cntlzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
#else
qemu_build_not_reached();
#endif
return true;
}