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ppc patch queue for 2020-11-24

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One final update for qemu-5.2, implementing an instruction that we
 already should have, given the ISA version we claim to support.  Sorry
 for the lateness, I've been on holiday.
 
 This isn't a regression, obviously, so if it misses qemu-5.2 it's not
 a disaster, but it would be nice to have.  The risk is low that it
 would break any existing instructions.
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Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-5.2-20201124' into staging

ppc patch queue for 2020-11-24

One final update for qemu-5.2, implementing an instruction that we
already should have, given the ISA version we claim to support.  Sorry
for the lateness, I've been on holiday.

This isn't a regression, obviously, so if it misses qemu-5.2 it's not
a disaster, but it would be nice to have.  The risk is low that it
would break any existing instructions.

# gpg: Signature made Tue 24 Nov 2020 05:50:29 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dg-gitlab/tags/ppc-for-5.2-20201124:
  ppc/translate: Implement lxvwsx opcode

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-11-24 13:33:43 +00:00
commit 82d469e139
2 changed files with 31 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
target/ppc/translate/vsx-impl.c.inc
View File

@ -139,6 +139,36 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
static void gen_lxvwsx(DisasContext *ctx)
{
TCGv EA;
TCGv_i32 data;
if (xT(ctx->opcode) < 32) {
if (unlikely(!ctx->vsx_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
} else {
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
}
gen_set_access_type(ctx, ACCESS_INT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
data = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_TEUL);
tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
tcg_temp_free(EA);
tcg_temp_free_i32(data);
}
static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
TCGv_i64 inh, TCGv_i64 inl)
{

1
target/ppc/translate/vsx-ops.c.inc
View File

@ -5,6 +5,7 @@ GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvwsx, 0x1F, 0x0C, 0x0B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),