target-arm queue:
* hw/arm/orangepi: check for potential NULL pointer when calling blk_is_available * hw/misc/allwinner-h3-dramc: enforce 64-bit multiply when calculating row mirror address * docs/conf.py: Raise ConfigError for bad Sphinx Python version * hw/arm/xlnx-zynqmp.c: Avoid memory leak in error-return path * hw/arm/xlnx-zynqmp.c: Add missing error-propagation code * target/arm: fix incorrect current EL bug in aarch32 exception emulation -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl6B9cIZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pQBD/9L9M02vXS54OaJba8TAhOP KM+2psCTwJOMS7r9NWUWUHUY4mHoQZurXb5yDt3XJwlBe3LTfBxU/Se4SGgbJ5OQ ETBm54IpBpdPfhHKF4UuckiBPCSg8DN5FWIXh9MslBrSPr/0BHfPfQfyvy21hm8w PV2TpLP27J1tYeZmnZ2cL0YMN2/dp/VmYJO0hE3o8SJPtLV7RrevYgcYzJ1J89uP HvX2hzQHyqgm0V+a9zKBdP7EsUZhxd7CYaBcTNmG2cukv/7srcaPs2fZw9KuzwsJ FlHnFQqJOOEhE4Ir6uj/IwD0dWf7sVFPunEssAy/YnQwgAbMRktSX9lQ/AkKMztt d3J+8X4ApIiysljBxtTtkT8JteCyPEisFumoKVx+lxn3hKhvRYdXlP1EZKreaLoz QbCJjlcO5+GLpn1BcBt4tWZ9cJPisHZZNbZlsaG5IMHGwFrH0NTxba261JQhLmWX a6InvekjwBMTY2rzFIxCkLFquZBal2t2H9salPaW26hcTAOPjGghHhpPqWkdXu0E t9P+NgCOLhi+oIVX8FGHDu5NQwbtSIUy1wwwP5AhKOeUXW+rHut/AQHS/BRq4XId relYucjsSdoMC9X1mrRHNWYPKaUBV+/0xQw29XKmoTlMkvvYZl13WNhWuvFV596U wapi0SFTN3VijDgr+TwVYw== =6mtl -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200330' into staging target-arm queue: * hw/arm/orangepi: check for potential NULL pointer when calling blk_is_available * hw/misc/allwinner-h3-dramc: enforce 64-bit multiply when calculating row mirror address * docs/conf.py: Raise ConfigError for bad Sphinx Python version * hw/arm/xlnx-zynqmp.c: Avoid memory leak in error-return path * hw/arm/xlnx-zynqmp.c: Add missing error-propagation code * target/arm: fix incorrect current EL bug in aarch32 exception emulation # gpg: Signature made Mon 30 Mar 2020 14:36:02 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200330: target/arm: fix incorrect current EL bug in aarch32 exception emulation hw/arm/xlnx-zynqmp.c: Add missing error-propagation code hw/arm/xlnx-zynqmp.c: Avoid memory leak in error-return path docs/conf.py: Raise ConfigError for bad Sphinx Python version hw/misc/allwinner-h3-dramc: enforce 64-bit multiply when calculating row mirror address hw/arm/orangepi: check for potential NULL pointer when calling blk_is_available Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
83019e81d1
@ -29,14 +29,15 @@
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import os
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import sys
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import sphinx
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from sphinx.errors import VersionRequirementError
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from sphinx.errors import ConfigError
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# Make Sphinx fail cleanly if using an old Python, rather than obscurely
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# failing because some code in one of our extensions doesn't work there.
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# Unfortunately this doesn't display very neatly (there's an unavoidable
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# Python backtrace) but at least the information gets printed...
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# In newer versions of Sphinx this will display nicely; in older versions
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# Sphinx will also produce a Python backtrace but at least the information
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# gets printed...
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if sys.version_info < (3,5):
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raise VersionRequirementError(
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raise ConfigError(
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"QEMU requires a Sphinx that uses Python 3.5 or better\n")
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# The per-manual conf.py will set qemu_docdir for a single-manual build;
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@ -104,7 +104,7 @@ static void orangepi_init(MachineState *machine)
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machine->ram);
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/* Load target kernel or start using BootROM */
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if (!machine->kernel_filename && blk_is_available(blk)) {
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if (!machine->kernel_filename && blk && blk_is_available(blk)) {
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/* Use Boot ROM to copy data from SD card to SRAM */
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allwinner_h3_bootrom_setup(h3, blk);
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}
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@ -520,7 +520,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
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for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
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char *bus_name = g_strdup_printf("sd-bus%d", i);
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char *bus_name;
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SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
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Object *sdhci = OBJECT(&s->sdhci[i]);
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@ -530,8 +530,20 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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* - eMMC Specification Version 4.51
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*/
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object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_uint(sdhci, UHS_I, "uhs", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(sdhci, true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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@ -541,6 +553,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
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/* Alias controller SD bus to the SoC itself */
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bus_name = g_strdup_printf("sd-bus%d", i);
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object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
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&error_abort);
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g_free(bus_name);
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@ -550,6 +563,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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gchar *bus_name;
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object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
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@ -564,6 +581,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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}
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object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
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@ -618,6 +639,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
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object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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@ -85,8 +85,8 @@ static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
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} else if (row_bits_actual) {
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/* Row bits not matching ram_size, install the rows mirror */
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hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +
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bank_bits)) * page_size);
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hwaddr row_mirror = s->ram_addr + ((1ULL << (row_bits_actual +
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bank_bits)) * page_size);
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memory_region_set_enabled(&s->row_mirror_alias, true);
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memory_region_set_address(&s->row_mirror_alias, row_mirror);
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@ -9172,7 +9172,6 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
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/* Change the CPU state so as to actually take the exception. */
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switch_mode(env, new_mode);
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new_el = arm_current_el(env);
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/*
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* For exceptions taken to AArch32 we must clear the SS bit in both
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@ -9184,6 +9183,10 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
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env->condexec_bits = 0;
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/* Switch to the new mode, and to the correct instruction set. */
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env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
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/* This must be after mode switching. */
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new_el = arm_current_el(env);
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/* Set new mode endianness */
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env->uncached_cpsr &= ~CPSR_E;
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if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
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