hw/misc/bcm2835_cprman: add sane reset values to the registers
Those reset values have been extracted from a Raspberry Pi 3 model B v1.2, using the 2020-08-20 version of raspios. The dump was done using the debugfs interface of the CPRMAN driver in Linux (under '/sys/kernel/debug/clk'). Each exposed clock tree stage (PLLs, channels and muxes) can be observed by reading the 'regdump' file (e.g. 'plla/regdump'). Those values are set by the Raspberry Pi firmware at boot time (Linux expects them to be set when it boots up). Some stages are not exposed by the Linux driver (e.g. the PLL B). For those, the reset values are unknown and left to 0 which implies a disabled output. Once booted in QEMU, the final clock tree is very similar to the one visible on real hardware. The differences come from some unimplemented devices for which the driver simply disable the corresponding clock. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel
Peter Maydell
parent
502960ca04
commit
83ad469547
@ -53,6 +53,17 @@
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/* PLL */
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static void pll_reset(DeviceState *dev)
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{
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CprmanPllState *s = CPRMAN_PLL(dev);
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const PLLResetInfo *info = &PLL_RESET_INFO[s->id];
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*s->reg_cm = info->cm;
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*s->reg_a2w_ctrl = info->a2w_ctrl;
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memcpy(s->reg_a2w_ana, info->a2w_ana, sizeof(info->a2w_ana));
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*s->reg_a2w_frac = info->a2w_frac;
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}
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static bool pll_is_locked(const CprmanPllState *pll)
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{
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return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN)
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@ -123,6 +134,7 @@ static void pll_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = pll_reset;
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dc->vmsd = &pll_vmstate;
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}
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@ -137,6 +149,14 @@ static const TypeInfo cprman_pll_info = {
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/* PLL channel */
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static void pll_channel_reset(DeviceState *dev)
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{
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CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(dev);
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const PLLChannelResetInfo *info = &PLL_CHANNEL_RESET_INFO[s->id];
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*s->reg_a2w_ctrl = info->a2w_ctrl;
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}
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static bool pll_channel_is_enabled(CprmanPllChannelState *channel)
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{
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/*
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@ -217,6 +237,7 @@ static void pll_channel_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = pll_channel_reset;
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dc->vmsd = &pll_channel_vmstate;
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}
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@ -295,6 +316,15 @@ static void clock_mux_src_update(void *opaque)
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clock_mux_update(s);
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}
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static void clock_mux_reset(DeviceState *dev)
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{
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CprmanClockMuxState *clock = CPRMAN_CLOCK_MUX(dev);
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const ClockMuxResetInfo *info = &CLOCK_MUX_RESET_INFO[clock->id];
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*clock->reg_ctl = info->cm_ctl;
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*clock->reg_div = info->cm_div;
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}
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static void clock_mux_init(Object *obj)
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{
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CprmanClockMuxState *s = CPRMAN_CLOCK_MUX(obj);
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@ -327,6 +357,7 @@ static void clock_mux_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = clock_mux_reset;
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dc->vmsd = &clock_mux_vmstate;
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}
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@ -747,4 +747,273 @@ static inline void set_clock_mux_init_info(BCM2835CprmanState *s,
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mux->frac_bits = CLOCK_MUX_INIT_INFO[id].frac_bits;
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}
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/*
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* Object reset info
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* Those values have been dumped from a Raspberry Pi 3 Model B v1.2 using the
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* clk debugfs interface in Linux.
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*/
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typedef struct PLLResetInfo {
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uint32_t cm;
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uint32_t a2w_ctrl;
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uint32_t a2w_ana[4];
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uint32_t a2w_frac;
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} PLLResetInfo;
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static const PLLResetInfo PLL_RESET_INFO[] = {
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[CPRMAN_PLLA] = {
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.cm = 0x0000008a,
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.a2w_ctrl = 0x0002103a,
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.a2w_frac = 0x00098000,
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.a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
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},
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[CPRMAN_PLLC] = {
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.cm = 0x00000228,
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.a2w_ctrl = 0x0002103e,
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.a2w_frac = 0x00080000,
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.a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
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},
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[CPRMAN_PLLD] = {
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.cm = 0x0000020a,
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.a2w_ctrl = 0x00021034,
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.a2w_frac = 0x00015556,
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.a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
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},
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[CPRMAN_PLLH] = {
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.cm = 0x00000000,
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.a2w_ctrl = 0x0002102d,
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.a2w_frac = 0x00000000,
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.a2w_ana = { 0x00900000, 0x0000000c, 0x00000000, 0x00000000 }
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},
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[CPRMAN_PLLB] = {
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/* unknown */
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.cm = 0x00000000,
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.a2w_ctrl = 0x00000000,
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.a2w_frac = 0x00000000,
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.a2w_ana = { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
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}
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};
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typedef struct PLLChannelResetInfo {
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/*
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* Even though a PLL channel has a CM register, it shares it with its
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* parent PLL. The parent already takes care of the reset value.
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*/
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uint32_t a2w_ctrl;
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} PLLChannelResetInfo;
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static const PLLChannelResetInfo PLL_CHANNEL_RESET_INFO[] = {
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[CPRMAN_PLLA_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
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[CPRMAN_PLLA_CHANNEL_CORE] = { .a2w_ctrl = 0x00000003 },
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[CPRMAN_PLLA_CHANNEL_PER] = { .a2w_ctrl = 0x00000000 }, /* unknown */
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[CPRMAN_PLLA_CHANNEL_CCP2] = { .a2w_ctrl = 0x00000100 },
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[CPRMAN_PLLC_CHANNEL_CORE2] = { .a2w_ctrl = 0x00000100 },
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[CPRMAN_PLLC_CHANNEL_CORE1] = { .a2w_ctrl = 0x00000100 },
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[CPRMAN_PLLC_CHANNEL_PER] = { .a2w_ctrl = 0x00000002 },
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[CPRMAN_PLLC_CHANNEL_CORE0] = { .a2w_ctrl = 0x00000002 },
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[CPRMAN_PLLD_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
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[CPRMAN_PLLD_CHANNEL_CORE] = { .a2w_ctrl = 0x00000004 },
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[CPRMAN_PLLD_CHANNEL_PER] = { .a2w_ctrl = 0x00000004 },
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[CPRMAN_PLLD_CHANNEL_DSI1] = { .a2w_ctrl = 0x00000100 },
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[CPRMAN_PLLH_CHANNEL_AUX] = { .a2w_ctrl = 0x00000004 },
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[CPRMAN_PLLH_CHANNEL_RCAL] = { .a2w_ctrl = 0x00000000 },
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[CPRMAN_PLLH_CHANNEL_PIX] = { .a2w_ctrl = 0x00000000 },
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[CPRMAN_PLLB_CHANNEL_ARM] = { .a2w_ctrl = 0x00000000 }, /* unknown */
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};
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typedef struct ClockMuxResetInfo {
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uint32_t cm_ctl;
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uint32_t cm_div;
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} ClockMuxResetInfo;
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static const ClockMuxResetInfo CLOCK_MUX_RESET_INFO[] = {
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[CPRMAN_CLOCK_GNRIC] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_VPU] = {
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.cm_ctl = 0x00000245,
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.cm_div = 0x00003000,
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},
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[CPRMAN_CLOCK_SYS] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_PERIA] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_PERII] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_H264] = {
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.cm_ctl = 0x00000244,
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.cm_div = 0x00003000,
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},
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[CPRMAN_CLOCK_ISP] = {
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.cm_ctl = 0x00000244,
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.cm_div = 0x00003000,
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},
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[CPRMAN_CLOCK_V3D] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_CAM0] = {
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.cm_ctl = 0x00000000,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_CAM1] = {
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.cm_ctl = 0x00000000,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_CCP2] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_DSI0E] = {
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.cm_ctl = 0x00000000,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_DSI0P] = {
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.cm_ctl = 0x00000000,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_DPI] = {
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.cm_ctl = 0x00000000,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_GP0] = {
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.cm_ctl = 0x00000200,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_GP1] = {
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.cm_ctl = 0x00000096,
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.cm_div = 0x00014000,
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},
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[CPRMAN_CLOCK_GP2] = {
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.cm_ctl = 0x00000291,
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.cm_div = 0x00249f00,
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},
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[CPRMAN_CLOCK_HSM] = {
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.cm_ctl = 0x00000000,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_OTP] = {
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.cm_ctl = 0x00000091,
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.cm_div = 0x00004000,
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},
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[CPRMAN_CLOCK_PCM] = {
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.cm_ctl = 0x00000200,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_PWM] = {
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.cm_ctl = 0x00000200,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_SLIM] = {
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.cm_ctl = 0x00000200,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_SMI] = {
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.cm_ctl = 0x00000000,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_TEC] = {
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.cm_ctl = 0x00000000,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_TD0] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_TD1] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_TSENS] = {
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.cm_ctl = 0x00000091,
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.cm_div = 0x0000a000,
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},
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[CPRMAN_CLOCK_TIMER] = {
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.cm_ctl = 0x00000291,
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.cm_div = 0x00013333,
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},
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[CPRMAN_CLOCK_UART] = {
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.cm_ctl = 0x00000296,
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.cm_div = 0x0000a6ab,
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},
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[CPRMAN_CLOCK_VEC] = {
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.cm_ctl = 0x00000097,
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.cm_div = 0x00002000,
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},
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[CPRMAN_CLOCK_PULSE] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_SDC] = {
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.cm_ctl = 0x00004006,
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.cm_div = 0x00003000,
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},
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[CPRMAN_CLOCK_ARM] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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[CPRMAN_CLOCK_AVEO] = {
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.cm_ctl = 0x00000000,
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.cm_div = 0x00000000,
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},
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[CPRMAN_CLOCK_EMMC] = {
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.cm_ctl = 0x00000295,
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.cm_div = 0x00006000,
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},
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[CPRMAN_CLOCK_EMMC2] = {
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.cm_ctl = 0, /* unknown */
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.cm_div = 0
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},
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};
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#endif
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