ac97: convert to memory API
fixes BAR sizing as well. Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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bd80f3fc00
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83c406d986
87
hw/ac97.c
87
hw/ac97.c
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@ -160,8 +160,9 @@ typedef struct AC97LinkState {
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SWVoiceIn *voice_mc;
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SWVoiceIn *voice_mc;
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int invalid_freq[3];
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int invalid_freq[3];
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uint8_t silence[128];
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uint8_t silence[128];
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uint32_t base[2];
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int bup_flag;
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int bup_flag;
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MemoryRegion io_nam;
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MemoryRegion io_nabm;
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} AC97LinkState;
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} AC97LinkState;
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enum {
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enum {
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@ -583,7 +584,7 @@ static uint32_t nam_readw (void *opaque, uint32_t addr)
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{
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{
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AC97LinkState *s = opaque;
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AC97LinkState *s = opaque;
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uint32_t val = ~0U;
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uint32_t val = ~0U;
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uint32_t index = addr - s->base[0];
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uint32_t index = addr;
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s->cas = 0;
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s->cas = 0;
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val = mixer_load (s, index);
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val = mixer_load (s, index);
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return val;
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return val;
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@ -611,7 +612,7 @@ static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
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static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
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static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
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{
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{
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AC97LinkState *s = opaque;
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AC97LinkState *s = opaque;
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uint32_t index = addr - s->base[0];
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uint32_t index = addr;
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s->cas = 0;
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s->cas = 0;
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switch (index) {
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switch (index) {
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case AC97_Reset:
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case AC97_Reset:
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@ -714,7 +715,7 @@ static uint32_t nabm_readb (void *opaque, uint32_t addr)
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{
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{
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AC97LinkState *s = opaque;
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AC97LinkState *s = opaque;
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AC97BusMasterRegs *r = NULL;
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AC97BusMasterRegs *r = NULL;
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uint32_t index = addr - s->base[1];
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uint32_t index = addr;
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uint32_t val = ~0U;
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uint32_t val = ~0U;
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switch (index) {
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switch (index) {
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@ -769,7 +770,7 @@ static uint32_t nabm_readw (void *opaque, uint32_t addr)
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{
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{
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AC97LinkState *s = opaque;
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AC97LinkState *s = opaque;
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AC97BusMasterRegs *r = NULL;
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AC97BusMasterRegs *r = NULL;
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uint32_t index = addr - s->base[1];
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uint32_t index = addr;
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uint32_t val = ~0U;
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uint32_t val = ~0U;
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switch (index) {
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switch (index) {
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@ -798,7 +799,7 @@ static uint32_t nabm_readl (void *opaque, uint32_t addr)
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{
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{
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AC97LinkState *s = opaque;
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AC97LinkState *s = opaque;
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AC97BusMasterRegs *r = NULL;
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AC97BusMasterRegs *r = NULL;
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uint32_t index = addr - s->base[1];
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uint32_t index = addr;
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uint32_t val = ~0U;
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uint32_t val = ~0U;
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switch (index) {
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switch (index) {
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@ -848,7 +849,7 @@ static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
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{
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{
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AC97LinkState *s = opaque;
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AC97LinkState *s = opaque;
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AC97BusMasterRegs *r = NULL;
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AC97BusMasterRegs *r = NULL;
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uint32_t index = addr - s->base[1];
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uint32_t index = addr;
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switch (index) {
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switch (index) {
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case PI_LVI:
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case PI_LVI:
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case PO_LVI:
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case PO_LVI:
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@ -904,7 +905,7 @@ static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
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{
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{
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AC97LinkState *s = opaque;
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AC97LinkState *s = opaque;
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AC97BusMasterRegs *r = NULL;
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AC97BusMasterRegs *r = NULL;
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uint32_t index = addr - s->base[1];
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uint32_t index = addr;
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switch (index) {
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switch (index) {
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case PI_SR:
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case PI_SR:
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case PO_SR:
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case PO_SR:
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@ -924,7 +925,7 @@ static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
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{
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{
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AC97LinkState *s = opaque;
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AC97LinkState *s = opaque;
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AC97BusMasterRegs *r = NULL;
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AC97BusMasterRegs *r = NULL;
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uint32_t index = addr - s->base[1];
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uint32_t index = addr;
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switch (index) {
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switch (index) {
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case PI_BDBAR:
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case PI_BDBAR:
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case PO_BDBAR:
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case PO_BDBAR:
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@ -1230,31 +1231,33 @@ static const VMStateDescription vmstate_ac97 = {
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}
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}
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};
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};
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static void ac97_map (PCIDevice *pci_dev, int region_num,
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static const MemoryRegionPortio nam_portio[] = {
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pcibus_t addr, pcibus_t size, int type)
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{ 0, 256 * 1, 1, .read = nam_readb, },
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{
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{ 0, 256 * 2, 2, .read = nam_readw, },
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AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev);
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{ 0, 256 * 4, 4, .read = nam_readl, },
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PCIDevice *d = &s->dev;
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{ 0, 256 * 1, 1, .write = nam_writeb, },
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{ 0, 256 * 2, 2, .write = nam_writew, },
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{ 0, 256 * 4, 4, .write = nam_writel, },
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PORTIO_END_OF_LIST(),
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};
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if (!region_num) {
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static const MemoryRegionOps ac97_io_nam_ops = {
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s->base[0] = addr;
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.old_portio = nam_portio,
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register_ioport_read (addr, 256 * 1, 1, nam_readb, d);
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};
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register_ioport_read (addr, 256 * 2, 2, nam_readw, d);
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register_ioport_read (addr, 256 * 4, 4, nam_readl, d);
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static const MemoryRegionPortio nabm_portio[] = {
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register_ioport_write (addr, 256 * 1, 1, nam_writeb, d);
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{ 0, 64 * 1, 1, .read = nabm_readb, },
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register_ioport_write (addr, 256 * 2, 2, nam_writew, d);
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{ 0, 64 * 2, 2, .read = nabm_readw, },
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register_ioport_write (addr, 256 * 4, 4, nam_writel, d);
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{ 0, 64 * 4, 4, .read = nabm_readl, },
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}
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{ 0, 64 * 1, 1, .write = nabm_writeb, },
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else {
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{ 0, 64 * 2, 2, .write = nabm_writew, },
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s->base[1] = addr;
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{ 0, 64 * 4, 4, .write = nabm_writel, },
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register_ioport_read (addr, 64 * 1, 1, nabm_readb, d);
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PORTIO_END_OF_LIST()
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register_ioport_read (addr, 64 * 2, 2, nabm_readw, d);
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};
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register_ioport_read (addr, 64 * 4, 4, nabm_readl, d);
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register_ioport_write (addr, 64 * 1, 1, nabm_writeb, d);
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static const MemoryRegionOps ac97_io_nabm_ops = {
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register_ioport_write (addr, 64 * 2, 2, nabm_writew, d);
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.old_portio = nabm_portio,
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register_ioport_write (addr, 64 * 4, 4, nabm_writel, d);
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};
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}
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}
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static void ac97_on_reset (void *opaque)
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static void ac97_on_reset (void *opaque)
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{
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{
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@ -1311,15 +1314,26 @@ static int ac97_initfn (PCIDevice *dev)
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/* TODO: RST# value should be 0. */
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/* TODO: RST# value should be 0. */
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c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
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c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
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pci_register_bar (&s->dev, 0, 256 * 4, PCI_BASE_ADDRESS_SPACE_IO,
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memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
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ac97_map);
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memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
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pci_register_bar (&s->dev, 1, 64 * 4, PCI_BASE_ADDRESS_SPACE_IO, ac97_map);
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pci_register_bar_region (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
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pci_register_bar_region (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO,
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&s->io_nabm);
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qemu_register_reset (ac97_on_reset, s);
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qemu_register_reset (ac97_on_reset, s);
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AUD_register_card ("ac97", &s->card);
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AUD_register_card ("ac97", &s->card);
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ac97_on_reset (s);
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ac97_on_reset (s);
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return 0;
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return 0;
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}
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}
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static int ac97_exitfn (PCIDevice *dev)
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{
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AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
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memory_region_destroy (&s->io_nam);
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memory_region_destroy (&s->io_nabm);
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return 0;
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}
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int ac97_init (PCIBus *bus)
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int ac97_init (PCIBus *bus)
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{
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{
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pci_create_simple (bus, -1, "AC97");
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pci_create_simple (bus, -1, "AC97");
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@ -1332,6 +1346,7 @@ static PCIDeviceInfo ac97_info = {
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.qdev.size = sizeof (AC97LinkState),
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.qdev.size = sizeof (AC97LinkState),
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.qdev.vmsd = &vmstate_ac97,
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.qdev.vmsd = &vmstate_ac97,
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.init = ac97_initfn,
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.init = ac97_initfn,
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.exit = ac97_exitfn,
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.vendor_id = PCI_VENDOR_ID_INTEL,
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.device_id = PCI_DEVICE_ID_INTEL_82801AA_5,
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.device_id = PCI_DEVICE_ID_INTEL_82801AA_5,
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.revision = 0x01,
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.revision = 0x01,
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