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pc: map PCI address space as catchall region for not mapped addresses

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With a help of negative memory region priority PCI address space
is mapped underneath RAM regions effectively catching every access
to addresses not mapped by any other region.
It simplifies PCI address space mapping into system address space.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
This commit is contained in:
Michael S. Tsirkin 2013-10-29 13:57:34 +01:00
parent e689f7c668
commit 83d08f2673
6 changed files with 14 additions and 71 deletions
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20
hw/i386/pc.c
View File

@ -1093,21 +1093,13 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
return guest_info;
}
void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
uint64_t pci_hole64_size)
/* setup pci memory address space mapping into system address space */
void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
MemoryRegion *pci_address_space)
{
if ((sizeof(hwaddr) == 4) || (!pci_hole64_size)) {
return;
}
/*
* BIOS does not set MTRR entries for the 64 bit window, so no need to
* align address to power of two. Align address at 1G, this makes sure
* it can be exactly covered with a PAT entry even when using huge
* pages.
*/
pci_info->w64.begin = ROUND_UP(pci_hole64_start, 0x1ULL << 30);
pci_info->w64.end = pci_info->w64.begin + pci_hole64_size;
assert(pci_info->w64.begin <= pci_info->w64.end);
/* Set to lower priority than RAM */
memory_region_add_subregion_overlap(system_memory, 0x0,
pci_address_space, -1);
}
void pc_acpi_init(const char *default_dsdt)

2
hw/i386/pc_piix.c
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@ -149,8 +149,6 @@ static void pc_init1(QEMUMachineInitArgs *args,
if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,
system_memory, system_io, args->ram_size,
below_4g_mem_size,
0x100000000ULL - below_4g_mem_size,
above_4g_mem_size,
pci_memory, ram_memory);
} else {

24
hw/pci-host/piix.c
View File

@ -103,8 +103,6 @@ struct PCII440FXState {
MemoryRegion *system_memory;
MemoryRegion *pci_address_space;
MemoryRegion *ram_memory;
MemoryRegion pci_hole;
MemoryRegion pci_hole_64bit;
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region;
uint8_t smm_enabled;
@ -313,8 +311,6 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
hwaddr pci_hole_start,
hwaddr pci_hole_size,
ram_addr_t above_4g_mem_size,
MemoryRegion *pci_address_space,
MemoryRegion *ram_memory)
@ -327,7 +323,6 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
PCII440FXState *f;
unsigned i;
I440FXState *i440fx;
uint64_t pci_hole64_size;
dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
s = PCI_HOST_BRIDGE(dev);
@ -355,23 +350,10 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
i440fx->pci_info.w32.begin = 0xe0000000;
}
memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space,
pci_hole_start, pci_hole_size);
memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
/* setup pci memory mapping */
pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
f->pci_address_space);
pci_hole64_size = pci_host_get_hole64_size(i440fx->pci_hole64_size);
pc_init_pci64_hole(&i440fx->pci_info, 0x100000000ULL + above_4g_mem_size,
pci_hole64_size);
memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64",
f->pci_address_space,
i440fx->pci_info.w64.begin,
pci_hole64_size);
if (pci_hole64_size) {
memory_region_add_subregion(f->system_memory,
i440fx->pci_info.w64.begin,
&f->pci_hole_64bit);
}
memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
f->pci_address_space, 0xa0000, 0x20000);
memory_region_add_subregion_overlap(f->system_memory, 0xa0000,

23
hw/pci-host/q35.c
View File

@ -356,28 +356,11 @@ static int mch_init(PCIDevice *d)
{
int i;
MCHPCIState *mch = MCH_PCI_DEVICE(d);
uint64_t pci_hole64_size;
/* setup pci memory regions */
memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole",
mch->pci_address_space,
mch->below_4g_mem_size,
0x100000000ULL - mch->below_4g_mem_size);
memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
&mch->pci_hole);
/* setup pci memory mapping */
pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
mch->pci_address_space);
pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size);
pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size,
pci_hole64_size);
memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64",
mch->pci_address_space,
mch->pci_info.w64.begin,
pci_hole64_size);
if (pci_hole64_size) {
memory_region_add_subregion(mch->system_memory,
mch->pci_info.w64.begin,
&mch->pci_hole_64bit);
}
/* smram */
cpu_smm_register(&mch_set_smm, mch);
memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",

14
include/hw/i386/pc.h
View File

@ -128,17 +128,9 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
{
if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
return 1ULL << 62;
} else {
return pci_hole64_size;
}
}
void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
uint64_t pci_hole64_size);
void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
MemoryRegion *pci_address_space);
FWCfgState *pc_memory_init(MemoryRegion *system_memory,
const char *kernel_filename,
@ -187,8 +179,6 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
hwaddr pci_hole_start,
hwaddr pci_hole_size,
ram_addr_t above_4g_mem_size,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);

2
include/hw/pci-host/q35.h
View File

@ -53,8 +53,6 @@ typedef struct MCHPCIState {
MemoryRegion *address_space_io;
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region;
MemoryRegion pci_hole;
MemoryRegion pci_hole_64bit;
PcPciInfo pci_info;
uint8_t smm_enabled;
ram_addr_t below_4g_mem_size;