target/arm: Honor the HCR_EL2.{TVM,TRVM} bits
These bits trap EL1 access to various virtual memory controls. Buglink: https://bugs.launchpad.net/bugs/1855072 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200229012811.24129-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
4990e1d3c1
commit
8492921851
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@ -530,6 +530,19 @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
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static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1) {
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uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
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if (arm_hcr_el2_eff(env) & trap) {
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return CP_ACCESS_TRAP_EL2;
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}
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}
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return CP_ACCESS_OK;
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}
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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@ -785,12 +798,14 @@ static const ARMCPRegInfo cp_reginfo[] = {
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*/
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{ .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
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.access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.secure = ARM_CP_SECSTATE_NS,
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.fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
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.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
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{ .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
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.access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.secure = ARM_CP_SECSTATE_S,
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.fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
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.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
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REGINFO_SENTINEL
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@ -803,7 +818,7 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
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/* MMU Domain access control / MPU write buffer control */
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{ .name = "DACR",
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.cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
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.access = PL1_RW, .resetvalue = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
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.writefn = dacr_write, .raw_writefn = raw_write,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
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offsetoflow32(CPUARMState, cp15.dacr_ns) } },
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@ -996,7 +1011,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
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{ .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
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.access = PL0_W, .type = ARM_CP_NOP },
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{ .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
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.access = PL1_RW,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
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offsetof(CPUARMState, cp15.ifar_ns) },
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.resetvalue = 0, },
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@ -2208,16 +2223,19 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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*/
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{ .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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/* MAIR can just read-as-written because we don't implement caches
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* and so don't need to care about memory attributes.
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*/
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{ .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
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.resetvalue = 0 },
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{ .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
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@ -2231,12 +2249,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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* handled in the field definitions.
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*/
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{ .name = "MAIR0", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
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.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
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offsetof(CPUARMState, cp15.mair0_ns) },
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.resetfn = arm_cp_reset_ignore },
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{ .name = "MAIR1", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
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.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
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offsetof(CPUARMState, cp15.mair1_ns) },
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.resetfn = arm_cp_reset_ignore },
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@ -3886,20 +3906,21 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
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{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_ALIAS,
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.access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
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offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
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{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .resetvalue = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
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offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
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{ .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .resetvalue = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
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offsetof(CPUARMState, cp15.dfar_ns) } },
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{ .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
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.resetvalue = 0, },
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REGINFO_SENTINEL
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};
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@ -3907,25 +3928,29 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
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static const ARMCPRegInfo vmsa_cp_reginfo[] = {
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{ .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
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{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.writefn = vmsa_ttbr_write, .resetvalue = 0,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
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offsetof(CPUARMState, cp15.ttbr0_ns) } },
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{ .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
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.access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.writefn = vmsa_ttbr_write, .resetvalue = 0,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
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offsetof(CPUARMState, cp15.ttbr1_ns) } },
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{ .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
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.access = PL1_RW, .writefn = vmsa_tcr_el12_write,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.writefn = vmsa_tcr_el12_write,
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.resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
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.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
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{ .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
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.access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
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.raw_writefn = vmsa_ttbcr_raw_write,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
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offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
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@ -3937,7 +3962,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
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*/
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static const ARMCPRegInfo ttbcr2_reginfo = {
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.name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_ALIAS,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_ALIAS,
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.bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
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offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
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};
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@ -4157,23 +4183,25 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
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/* NOP AMAIR0/1 */
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{ .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST,
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.resetvalue = 0 },
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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/* AMAIR1 is mapped to AMAIR_EL1[63:32] */
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{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST,
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.resetvalue = 0 },
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
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.access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
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offsetof(CPUARMState, cp15.par_ns)} },
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{ .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
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.access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_64BIT | ARM_CP_ALIAS,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
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offsetof(CPUARMState, cp15.ttbr0_ns) },
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.writefn = vmsa_ttbr_write, },
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{ .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
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.access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.type = ARM_CP_64BIT | ARM_CP_ALIAS,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
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offsetof(CPUARMState, cp15.ttbr1_ns) },
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.writefn = vmsa_ttbr_write, },
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@ -4888,7 +4916,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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.type = ARM_CP_NOP, .access = PL1_W },
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/* MMU Domain access control / MPU write buffer control */
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{ .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .resetvalue = 0,
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.access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
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.writefn = dacr_write, .raw_writefn = raw_write,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
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offsetoflow32(CPUARMState, cp15.dacr_ns) } },
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@ -7765,7 +7793,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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ARMCPRegInfo sctlr = {
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.name = "SCTLR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
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.access = PL1_RW,
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.access = PL1_RW, .accessfn = access_tvm_trvm,
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.bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
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offsetof(CPUARMState, cp15.sctlr_ns) },
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.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
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