target/arm: Add support for FEAT_TLBIRANGE
ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI maintenance instructions that apply to a range of input addresses. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210512182337.18563-2-rebecca@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rebecca Cran
Peter Maydell
parent
206a583d13
commit
84940ed825
@ -4071,6 +4071,11 @@ static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
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}
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static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
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}
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static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
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@ -4759,6 +4759,172 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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ARMMMUIdxBit_SE3, bits);
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}
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#ifdef TARGET_AARCH64
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static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
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uint64_t value)
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{
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unsigned int page_shift;
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unsigned int page_size_granule;
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uint64_t num;
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uint64_t scale;
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uint64_t exponent;
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uint64_t length;
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num = extract64(value, 39, 4);
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scale = extract64(value, 44, 2);
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page_size_granule = extract64(value, 46, 2);
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page_shift = page_size_granule * 2 + 12;
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if (page_size_granule == 0) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
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page_size_granule);
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return 0;
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}
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exponent = (5 * scale) + 1;
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length = (num + 1) << (exponent + page_shift);
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return length;
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}
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static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value,
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bool two_ranges)
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{
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/* TODO: ARMv8.7 FEAT_LPA2 */
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uint64_t pageaddr;
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if (two_ranges) {
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pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
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} else {
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pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS;
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}
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return pageaddr;
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}
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static void do_rvae_write(CPUARMState *env, uint64_t value,
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int idxmap, bool synced)
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{
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ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap);
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bool two_ranges = regime_has_2_ranges(one_idx);
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uint64_t baseaddr, length;
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int bits;
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baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges);
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length = tlbi_aa64_range_get_length(env, value);
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bits = tlbbits_for_regime(env, one_idx, baseaddr);
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if (synced) {
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tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
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baseaddr,
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length,
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idxmap,
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bits);
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} else {
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tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr,
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length, idxmap, bits);
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}
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}
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static void tlbi_aa64_rvae1_write(CPUARMState *env,
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const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/*
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* Invalidate by VA range, EL1&0.
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* Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
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* since we don't support flush-for-specific-ASID-only or
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* flush-last-level-only.
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*/
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do_rvae_write(env, value, vae1_tlbmask(env),
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tlb_force_broadcast(env));
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}
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static void tlbi_aa64_rvae1is_write(CPUARMState *env,
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const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/*
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* Invalidate by VA range, Inner/Outer Shareable EL1&0.
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* Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
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* RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
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* flush-for-specific-ASID-only, flush-last-level-only or inner/outer
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* shareable specific flushes.
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*/
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do_rvae_write(env, value, vae1_tlbmask(env), true);
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}
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static int vae2_tlbmask(CPUARMState *env)
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{
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return (arm_is_secure_below_el3(env)
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? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2);
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}
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static void tlbi_aa64_rvae2_write(CPUARMState *env,
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const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/*
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* Invalidate by VA range, EL2.
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* Currently handles all of RVAE2 and RVALE2,
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* since we don't support flush-for-specific-ASID-only or
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* flush-last-level-only.
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*/
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do_rvae_write(env, value, vae2_tlbmask(env),
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tlb_force_broadcast(env));
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}
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static void tlbi_aa64_rvae2is_write(CPUARMState *env,
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const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/*
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* Invalidate by VA range, Inner/Outer Shareable, EL2.
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* Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
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* since we don't support flush-for-specific-ASID-only,
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* flush-last-level-only or inner/outer shareable specific flushes.
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*/
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do_rvae_write(env, value, vae2_tlbmask(env), true);
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}
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static void tlbi_aa64_rvae3_write(CPUARMState *env,
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const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/*
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* Invalidate by VA range, EL3.
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* Currently handles all of RVAE3 and RVALE3,
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* since we don't support flush-for-specific-ASID-only or
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* flush-last-level-only.
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*/
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do_rvae_write(env, value, ARMMMUIdxBit_SE3,
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tlb_force_broadcast(env));
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}
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static void tlbi_aa64_rvae3is_write(CPUARMState *env,
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const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/*
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* Invalidate by VA range, EL3, Inner/Outer Shareable.
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* Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
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* since we don't support flush-for-specific-ASID-only,
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* flush-last-level-only or inner/outer specific flushes.
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*/
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do_rvae_write(env, value, ARMMMUIdxBit_SE3, true);
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}
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#endif
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static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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@ -6920,6 +7086,118 @@ static const ARMCPRegInfo pauth_reginfo[] = {
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REGINFO_SENTINEL
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};
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static const ARMCPRegInfo tlbirange_reginfo[] = {
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{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1is_write },
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{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1_write },
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{ .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1_write },
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{ .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1_write },
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{ .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
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.access = PL1_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae1_write },
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{ .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
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.access = PL2_W, .type = ARM_CP_NOP },
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{ .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6,
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.access = PL2_W, .type = ARM_CP_NOP },
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{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae2is_write },
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{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae2is_write },
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{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
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.access = PL2_W, .type = ARM_CP_NOP },
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{ .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6,
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.access = PL2_W, .type = ARM_CP_NOP },
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{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae2is_write },
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{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae2is_write },
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{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae2_write },
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{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
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.access = PL2_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae2_write },
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{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae3is_write },
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{ .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae3is_write },
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{ .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae3is_write },
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{ .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae3is_write },
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{ .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae3_write },
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{ .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64,
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.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5,
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.access = PL3_W, .type = ARM_CP_NO_RAW,
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.writefn = tlbi_aa64_rvae3_write },
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REGINFO_SENTINEL
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};
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static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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Error *err = NULL;
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@ -8289,6 +8567,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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if (cpu_isar_feature(aa64_rndr, cpu)) {
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define_arm_cp_regs(cpu, rndr_reginfo);
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}
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if (cpu_isar_feature(aa64_tlbirange, cpu)) {
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define_arm_cp_regs(cpu, tlbirange_reginfo);
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}
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#ifndef CONFIG_USER_ONLY
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/* Data Cache clean instructions up to PoP */
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if (cpu_isar_feature(aa64_dcpop, cpu)) {
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