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target/hppa: Decode d for bb instructions

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Manipulate the shift count so that the bit to be tested
is always placed at the MSB.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-16 21:41:32 -07:00
parent 63c427c615
commit 84e224d422
2 changed files with 4 additions and 6 deletions
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4
target/hppa/insns.decode
View File

@ -290,8 +290,8 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
# Conditional Branches
####
bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12
bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12
bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
movbi 110011 ..... ..... ... ........... . . @rib_cf f=0

6
target/hppa/translate.c
View File

@ -3172,13 +3172,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
bool d = false;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
if (cond_need_ext(ctx, d)) {
if (cond_need_ext(ctx, a->d)) {
/* Force shift into [32,63] */
tcg_gen_ori_reg(tmp, cpu_sar, 32);
tcg_gen_shl_reg(tmp, tcg_r, tmp);
@ -3194,14 +3193,13 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
bool d = false;
int p;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
p = a->p | (cond_need_ext(ctx, d) ? 32 : 0);
p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0);
tcg_gen_shli_reg(tmp, tcg_r, p);
cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);