diff --git a/cpu-all.h b/cpu-all.h
index 39dfa464ba..54df1d323c 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -826,10 +826,6 @@ extern CPUState *cpu_single_env;
 
 /* First unused bit: 0x2000.  */
 
-/* Temporary remapping from the generic names back to the previous
-   cpu-specific names.  These will be moved to target-foo/cpu.h next.  */
-#define CPU_INTERRUPT_NMI         CPU_INTERRUPT_TGT_EXT_3
-
 /* The set of all bits that should be masked when single-stepping.  */
 #define CPU_INTERRUPT_SSTEP_MASK \
     (CPU_INTERRUPT_HARD          \
diff --git a/poison.h b/poison.h
index 4fcf46dcf1..2b182328a1 100644
--- a/poison.h
+++ b/poison.h
@@ -41,7 +41,6 @@
 #pragma GCC poison CPU_INTERRUPT_EXITTB
 #pragma GCC poison CPU_INTERRUPT_HALT
 #pragma GCC poison CPU_INTERRUPT_DEBUG
-#pragma GCC poison CPU_INTERRUPT_NMI
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_2
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index d9087759d3..8686dbaf2e 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -36,6 +36,9 @@
 #define EXCP_IRQ        4
 #define EXCP_BREAK      5
 
+/* CRIS-specific interrupt pending bits.  */
+#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
+
 /* Register aliases. R0 - R15 */
 #define R_FP  8
 #define R_SP  14
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 1fc421f6ac..715828f2df 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -468,6 +468,7 @@
 
 /* i386-specific interrupt pending bits.  */
 #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
+#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
 #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
 #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_TGT_INT_1
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 536222e4b8..78fe14ff35 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -41,6 +41,9 @@ struct CPUMBState;
 #define EXCP_HW_BREAK   5
 #define EXCP_HW_EXCP    6
 
+/* MicroBlaze-specific interrupt pending bits.  */
+#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
+
 /* Register aliases. R0 - R15 */
 #define R_SP     1
 #define SR_PC    0