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irq: Privatize CPU_INTERRUPT_NMI.

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This interrupt name is used by i386, CRIS, and MicroBlaze.
Copy the name into each target.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson 2011-05-04 13:34:31 -07:00 committed by Blue Swirl
parent 00a152b48b
commit 85097db695
5 changed files with 7 additions and 5 deletions
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4
cpu-all.h
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@ -826,10 +826,6 @@ extern CPUState *cpu_single_env;
/* First unused bit: 0x2000. */ /* First unused bit: 0x2000. */
/* Temporary remapping from the generic names back to the previous
cpu-specific names. These will be moved to target-foo/cpu.h next. */
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
/* The set of all bits that should be masked when single-stepping. */ /* The set of all bits that should be masked when single-stepping. */
#define CPU_INTERRUPT_SSTEP_MASK \ #define CPU_INTERRUPT_SSTEP_MASK \
(CPU_INTERRUPT_HARD \ (CPU_INTERRUPT_HARD \

1
poison.h
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@ -41,7 +41,6 @@
#pragma GCC poison CPU_INTERRUPT_EXITTB #pragma GCC poison CPU_INTERRUPT_EXITTB
#pragma GCC poison CPU_INTERRUPT_HALT #pragma GCC poison CPU_INTERRUPT_HALT
#pragma GCC poison CPU_INTERRUPT_DEBUG #pragma GCC poison CPU_INTERRUPT_DEBUG
#pragma GCC poison CPU_INTERRUPT_NMI
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2 #pragma GCC poison CPU_INTERRUPT_TGT_EXT_2

3
target-cris/cpu.h
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@ -36,6 +36,9 @@
#define EXCP_IRQ 4 #define EXCP_IRQ 4
#define EXCP_BREAK 5 #define EXCP_BREAK 5
/* CRIS-specific interrupt pending bits. */
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
/* Register aliases. R0 - R15 */ /* Register aliases. R0 - R15 */
#define R_FP 8 #define R_FP 8
#define R_SP 14 #define R_SP 14

1
target-i386/cpu.h
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@ -468,6 +468,7 @@
/* i386-specific interrupt pending bits. */ /* i386-specific interrupt pending bits. */
#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1

3
target-microblaze/cpu.h
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@ -41,6 +41,9 @@ struct CPUMBState;
#define EXCP_HW_BREAK 5 #define EXCP_HW_BREAK 5
#define EXCP_HW_EXCP 6 #define EXCP_HW_EXCP 6
/* MicroBlaze-specific interrupt pending bits. */
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
/* Register aliases. R0 - R15 */ /* Register aliases. R0 - R15 */
#define R_SP 1 #define R_SP 1
#define SR_PC 0 #define SR_PC 0