SH: Improve movca.l/ocbi emulation.
Author: Vladimir Prus <vladimir@codesourcery.com>
Fix movcal.l/ocbi emulation.
* target-sh4/cpu.h (memory_content): New.
(CPUSH4State): New fields movcal_backup and movcal_backup_tail.
* target-sh4/helper.h (helper_movcal)
(helper_discard_movcal_backup, helper_ocbi): New.
* target-sh4/op_helper.c (helper_movcal)
(helper_discard_movcal_backup, helper_ocbi): New.
* target-sh4/translate.c (DisasContext): New field has_movcal.
(sh4_defs): Update CVS for SH7785.
(cpu_sh4_init): Initialize env->movcal_backup_tail.
(_decode_opc): Discard movca.l-backup.
Make use of helper_movcal and helper_ocbi.
(gen_intermediate_code_internal): Initialize has_movcal to 1.
Thanks to Shin-ichiro KAWASAKI and Paul Mundt for valuable feedback.
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6966 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
714fa308a3
commit
852d481faf
@ -100,6 +100,12 @@ enum sh_features {
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SH_FEATURE_BCR3_AND_BCR4 = 2,
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};
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typedef struct memory_content {
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uint32_t address;
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uint32_t value;
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struct memory_content *next;
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} memory_content;
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typedef struct CPUSH4State {
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int id; /* CPU model */
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@ -148,6 +154,8 @@ typedef struct CPUSH4State {
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tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
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void *intc_handle;
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int intr_at_halt; /* SR_BL ignored during sleep */
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memory_content *movcal_backup;
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memory_content **movcal_backup_tail;
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} CPUSH4State;
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CPUSH4State *cpu_sh4_init(const char *cpu_model);
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@ -162,6 +170,8 @@ void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
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void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
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uint32_t mem_value);
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int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
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static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
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{
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env->gbr = newtls;
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@ -293,6 +303,8 @@ static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
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env->flags = tb->flags;
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}
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#define TB_FLAG_PENDING_MOVCA (1 << 4)
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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@ -302,7 +314,8 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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| DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
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| (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
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| (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */
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| (env->sr & SR_FD); /* Bit 15 */
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| (env->sr & SR_FD) /* Bit 15 */
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| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
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}
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#endif /* _CPU_SH4_H */
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@ -644,4 +644,48 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
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}
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}
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int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
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{
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int n;
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int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
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/* check area */
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if (env->sr & SR_MD) {
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/* For previledged mode, P2 and P4 area is not cachable. */
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if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
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return 0;
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} else {
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/* For user mode, only U0 area is cachable. */
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if (0x80000000 <= addr)
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return 0;
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}
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/*
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* TODO : Evaluate CCR and check if the cache is on or off.
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* Now CCR is not in CPUSH4State, but in SH7750State.
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* When you move the ccr inot CPUSH4State, the code will be
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* as follows.
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*/
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#if 0
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/* check if operand cache is enabled or not. */
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if (!(env->ccr & 1))
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return 0;
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#endif
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/* if MMU is off, no check for TLB. */
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if (env->mmucr & MMUCR_AT)
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return 1;
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/* check TLB */
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n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
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if (n >= 0)
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return env->itlb[n].c;
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n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
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if (n >= 0)
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return env->utlb[n].c;
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return 0;
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}
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#endif
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@ -9,6 +9,10 @@ DEF_HELPER_0(debug, void)
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DEF_HELPER_1(sleep, void, i32)
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DEF_HELPER_1(trapa, void, i32)
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DEF_HELPER_2(movcal, void, i32, i32)
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DEF_HELPER_0(discard_movcal_backup, void)
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DEF_HELPER_1(ocbi, void, i32)
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DEF_HELPER_2(addv, i32, i32, i32)
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DEF_HELPER_2(addc, i32, i32, i32)
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DEF_HELPER_2(subv, i32, i32, i32)
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@ -18,6 +18,7 @@
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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*/
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#include <assert.h>
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#include <stdlib.h>
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#include "exec.h"
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#include "helper.h"
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@ -122,6 +123,57 @@ void helper_trapa(uint32_t tra)
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cpu_loop_exit();
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}
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void helper_movcal(uint32_t address, uint32_t value)
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{
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if (cpu_sh4_is_cached (env, address))
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{
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memory_content *r = malloc (sizeof(memory_content));
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r->address = address;
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r->value = value;
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r->next = NULL;
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*(env->movcal_backup_tail) = r;
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env->movcal_backup_tail = &(r->next);
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}
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}
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void helper_discard_movcal_backup(void)
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{
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memory_content *current = env->movcal_backup;
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while(current)
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{
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memory_content *next = current->next;
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free (current);
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env->movcal_backup = current = next;
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if (current == 0)
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env->movcal_backup_tail = &(env->movcal_backup);
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}
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}
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void helper_ocbi(uint32_t address)
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{
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memory_content **current = &(env->movcal_backup);
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while (*current)
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{
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uint32_t a = (*current)->address;
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if ((a & ~0x1F) == (address & ~0x1F))
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{
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memory_content *next = (*current)->next;
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stl(a, (*current)->value);
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if (next == 0)
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{
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env->movcal_backup_tail = current;
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}
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free (*current);
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*current = next;
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break;
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}
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}
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}
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uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
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{
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uint32_t tmp0, tmp1;
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@ -50,6 +50,7 @@ typedef struct DisasContext {
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uint32_t delayed_pc;
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int singlestep_enabled;
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uint32_t features;
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int has_movcal;
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} DisasContext;
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#if defined(CONFIG_USER_ONLY)
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@ -283,6 +284,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model)
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env = qemu_mallocz(sizeof(CPUSH4State));
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env->features = def->features;
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cpu_exec_init(env);
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env->movcal_backup_tail = &(env->movcal_backup);
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sh4_translate_init();
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env->cpu_model_str = cpu_model;
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cpu_sh4_reset(env);
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@ -495,6 +497,37 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
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static void _decode_opc(DisasContext * ctx)
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{
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/* This code tries to make movcal emulation sufficiently
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accurate for Linux purposes. This instruction writes
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memory, and prior to that, always allocates a cache line.
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It is used in two contexts:
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- in memcpy, where data is copied in blocks, the first write
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of to a block uses movca.l for performance.
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- in arch/sh/mm/cache-sh4.c, movcal.l + ocbi combination is used
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to flush the cache. Here, the data written by movcal.l is never
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written to memory, and the data written is just bogus.
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To simulate this, we simulate movcal.l, we store the value to memory,
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but we also remember the previous content. If we see ocbi, we check
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if movcal.l for that address was done previously. If so, the write should
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not have hit the memory, so we restore the previous content.
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When we see an instruction that is neither movca.l
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nor ocbi, the previous content is discarded.
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To optimize, we only try to flush stores when we're at the start of
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TB, or if we already saw movca.l in this TB and did not flush stores
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yet. */
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if (ctx->has_movcal)
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{
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int opcode = ctx->opcode & 0xf0ff;
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if (opcode != 0x0093 /* ocbi */
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&& opcode != 0x00c3 /* movca.l */)
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{
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gen_helper_discard_movcal_backup ();
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ctx->has_movcal = 0;
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}
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}
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#if 0
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fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
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#endif
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@ -1545,7 +1578,13 @@ static void _decode_opc(DisasContext * ctx)
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}
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return;
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case 0x00c3: /* movca.l R0,@Rm */
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tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
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{
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TCGv val = tcg_temp_new();
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tcg_gen_qemu_ld32u(val, REG(B11_8), ctx->memidx);
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gen_helper_movcal (REG(B11_8), val);
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tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
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}
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ctx->has_movcal = 1;
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return;
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case 0x40a9:
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/* MOVUA.L @Rm,R0 (Rm) -> R0
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@ -1594,9 +1633,7 @@ static void _decode_opc(DisasContext * ctx)
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break;
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case 0x0093: /* ocbi @Rn */
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{
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TCGv dummy = tcg_temp_new();
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tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
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tcg_temp_free(dummy);
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gen_helper_ocbi (REG(B11_8));
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}
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return;
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case 0x00a3: /* ocbp @Rn */
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@ -1876,6 +1913,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
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ctx.tb = tb;
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ctx.singlestep_enabled = env->singlestep_enabled;
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ctx.features = env->features;
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ctx.has_movcal = (tb->flags & TB_FLAG_PENDING_MOVCA);
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#ifdef DEBUG_DISAS
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qemu_log_mask(CPU_LOG_TB_CPU,
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