OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

pull-loongarch-20240322

Browse Source 
-----BEGIN PGP SIGNATURE-----
 
 iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZf1WZgAKCRBAov/yOSY+
 35zZBADDPLM3130Q/2zsGhol1C538i4+hYRbrX+OsLnlaldyE3NqCPcgaKwVE3xS
 T9aOln91rDyQedz4DVYYSx+Oa1JpRjGko957REmopL50SJOYi6n7YhHJksaUirjJ
 tMDZdPClOegieOpCu8LgJAVhaxTpZvfLedJVPt7O6Fl/uP3pLg==
 =XLqh
 -----END PGP SIGNATURE-----

Merge tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20240322

# -----BEGIN PGP SIGNATURE-----
#
# iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZf1WZgAKCRBAov/yOSY+
# 35zZBADDPLM3130Q/2zsGhol1C538i4+hYRbrX+OsLnlaldyE3NqCPcgaKwVE3xS
# T9aOln91rDyQedz4DVYYSx+Oa1JpRjGko957REmopL50SJOYi6n7YhHJksaUirjJ
# tMDZdPClOegieOpCu8LgJAVhaxTpZvfLedJVPt7O6Fl/uP3pLg==
# =XLqh
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 22 Mar 2024 09:59:02 GMT
# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C  6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu:
  target/loongarch: Fix qemu-system-loongarch64 assert failed with the option '-d int'

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-03-22 10:59:57 +00:00
commit 853546f812
1 changed files with 40 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
target/loongarch/cpu.c
View File

@ -45,33 +45,45 @@ const char * const fregnames[32] = {
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
}; };
static const char * const excp_names[] = { struct TypeExcp {
[EXCCODE_INT] = "Interrupt", int32_t exccode;
[EXCCODE_PIL] = "Page invalid exception for load", const char * const name;
[EXCCODE_PIS] = "Page invalid exception for store", };
[EXCCODE_PIF] = "Page invalid exception for fetch",
[EXCCODE_PME] = "Page modified exception", static const struct TypeExcp excp_names[] = {
[EXCCODE_PNR] = "Page Not Readable exception", {EXCCODE_INT, "Interrupt"},
[EXCCODE_PNX] = "Page Not Executable exception", {EXCCODE_PIL, "Page invalid exception for load"},
[EXCCODE_PPI] = "Page Privilege error", {EXCCODE_PIS, "Page invalid exception for store"},
[EXCCODE_ADEF] = "Address error for instruction fetch", {EXCCODE_PIF, "Page invalid exception for fetch"},
[EXCCODE_ADEM] = "Address error for Memory access", {EXCCODE_PME, "Page modified exception"},
[EXCCODE_SYS] = "Syscall", {EXCCODE_PNR, "Page Not Readable exception"},
[EXCCODE_BRK] = "Break", {EXCCODE_PNX, "Page Not Executable exception"},
[EXCCODE_INE] = "Instruction Non-Existent", {EXCCODE_PPI, "Page Privilege error"},
[EXCCODE_IPE] = "Instruction privilege error", {EXCCODE_ADEF, "Address error for instruction fetch"},
[EXCCODE_FPD] = "Floating Point Disabled", {EXCCODE_ADEM, "Address error for Memory access"},
[EXCCODE_FPE] = "Floating Point Exception", {EXCCODE_SYS, "Syscall"},
[EXCCODE_DBP] = "Debug breakpoint", {EXCCODE_BRK, "Break"},
[EXCCODE_BCE] = "Bound Check Exception", {EXCCODE_INE, "Instruction Non-Existent"},
[EXCCODE_SXD] = "128 bit vector instructions Disable exception", {EXCCODE_IPE, "Instruction privilege error"},
[EXCCODE_ASXD] = "256 bit vector instructions Disable exception", {EXCCODE_FPD, "Floating Point Disabled"},
{EXCCODE_FPE, "Floating Point Exception"},
{EXCCODE_DBP, "Debug breakpoint"},
{EXCCODE_BCE, "Bound Check Exception"},
{EXCCODE_SXD, "128 bit vector instructions Disable exception"},
{EXCCODE_ASXD, "256 bit vector instructions Disable exception"},
{EXCP_HLT, "EXCP_HLT"},
}; };
const char *loongarch_exception_name(int32_t exception) const char *loongarch_exception_name(int32_t exception)
{ {
assert(excp_names[exception]); int i;
return excp_names[exception];
for (i = 0; i < ARRAY_SIZE(excp_names); i++) {
if (excp_names[i].exccode == exception) {
return excp_names[i].name;
}
}
return "Unknown";
} }
void G_NORETURN do_raise_exception(CPULoongArchState *env, void G_NORETURN do_raise_exception(CPULoongArchState *env,
@ -80,7 +92,7 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env,
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n", qemu_log_mask(CPU_LOG_INT, "%s: expection: %d (%s)\n",
__func__, __func__,
exception, exception,
loongarch_exception_name(exception)); loongarch_exception_name(exception));
@ -154,22 +166,16 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
CPULoongArchState *env = cpu_env(cs); CPULoongArchState *env = cpu_env(cs);
bool update_badinstr = 1; bool update_badinstr = 1;
int cause = -1; int cause = -1;
const char *name;
bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR); bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS); uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
if (cs->exception_index != EXCCODE_INT) { if (cs->exception_index != EXCCODE_INT) {
if (cs->exception_index < 0 ||
cs->exception_index >= ARRAY_SIZE(excp_names)) {
name = "unknown";
} else {
name = excp_names[cs->exception_index];
}
qemu_log_mask(CPU_LOG_INT, qemu_log_mask(CPU_LOG_INT,
"%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx "%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
" TLBRERA " TARGET_FMT_lx " %s exception\n", __func__, " TLBRERA " TARGET_FMT_lx " exception: %d (%s)\n",
env->pc, env->CSR_ERA, env->CSR_TLBRERA, name); __func__, env->pc, env->CSR_ERA, env->CSR_TLBRERA,
cs->exception_index,
loongarch_exception_name(cs->exception_index));
} }
switch (cs->exception_index) { switch (cs->exception_index) {