accel/tcg: Adjust cpu_signal_handler for NetBSD/arm
Fix building on NetBSD/arm by extracting the FSR value from the correct siginfo_t field. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20200516154147.24842-1-skrll@netbsd.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -517,6 +517,7 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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#if defined(__NetBSD__)
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#include <ucontext.h>
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#include <sys/siginfo.h>
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#endif
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int cpu_signal_handler(int host_signum, void *pinfo,
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@ -525,10 +526,12 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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siginfo_t *info = pinfo;
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#if defined(__NetBSD__)
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ucontext_t *uc = puc;
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siginfo_t *si = pinfo;
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#else
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ucontext_t *uc = puc;
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#endif
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unsigned long pc;
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uint32_t fsr;
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int is_write;
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#if defined(__NetBSD__)
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@ -539,10 +542,17 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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pc = uc->uc_mcontext.arm_pc;
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#endif
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/* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
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* later processor; on v5 we will always report this as a read).
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#ifdef __NetBSD__
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fsr = si->si_trap;
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#else
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fsr = uc->uc_mcontext.error_code;
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#endif
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/*
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* In the FSR, bit 11 is WnR, assuming a v6 or
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* later processor. On v5 we will always report
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* this as a read, which will fail later.
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*/
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is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
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is_write = extract32(fsr, 11, 1);
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return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
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}
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