apic: convert to qdev
Convert to qdev. Use an opaque CPUState pointer because of missing VMState implementation for CPUState. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Blue Swirl
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0e26b7b892
commit
8546b09965
94
hw/apic.c
94
hw/apic.c
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@ -17,13 +17,11 @@
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h"
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#include "pc.h"
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#include "apic.h"
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#include "pci.h"
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#include "msix.h"
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#include "qemu-timer.h"
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#include "host-utils.h"
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#include "kvm.h"
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#include "sysbus.h"
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//#define DEBUG_APIC
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//#define DEBUG_COALESCING
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@ -95,7 +93,8 @@
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#define MSI_ADDR_SIZE 0x100000
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struct APICState {
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CPUState *cpu_env;
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SysBusDevice busdev;
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void *cpu_env;
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uint32_t apicbase;
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uint8_t id;
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uint8_t arb_id;
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@ -120,12 +119,9 @@ struct APICState {
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int wait_for_sipi;
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};
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static int apic_io_memory;
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static APICState *local_apics[MAX_APICS + 1];
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static int last_apic_idx = 0;
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static int apic_irq_delivered;
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
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static void apic_update_irq(APICState *s);
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
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@ -930,9 +926,9 @@ static const VMStateDescription vmstate_apic = {
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}
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};
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static void apic_reset(void *opaque)
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static void apic_reset(DeviceState *d)
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{
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APICState *s = opaque;
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APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
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int bsp;
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bsp = cpu_is_bsp(s->cpu_env);
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@ -963,35 +959,71 @@ static CPUWriteMemoryFunc * const apic_mem_write[3] = {
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apic_mem_writel,
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};
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APICState *apic_init(CPUState *env, uint32_t apic_id)
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APICState *apic_init(void *env, uint8_t apic_id)
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{
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DeviceState *dev;
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SysBusDevice *d;
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APICState *s;
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static int apic_mapped;
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if (last_apic_idx >= MAX_APICS) {
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return NULL;
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dev = qdev_create(NULL, "apic");
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qdev_prop_set_uint8(dev, "id", apic_id);
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qdev_prop_set_ptr(dev, "cpu_env", env);
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qdev_init_nofail(dev);
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d = sysbus_from_qdev(dev);
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/* XXX: mapping more APICs at the same memory location */
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if (apic_mapped == 0) {
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/* NOTE: the APIC is directly connected to the CPU - it is not
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on the global memory bus. */
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/* XXX: what if the base changes? */
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sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
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apic_mapped = 1;
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}
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s = qemu_mallocz(sizeof(APICState));
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s->idx = last_apic_idx++;
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s->id = apic_id;
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s->cpu_env = env;
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msix_supported = 1;
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/* XXX: mapping more APICs at the same memory location */
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if (apic_io_memory == 0) {
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/* NOTE: the APIC is directly connected to the CPU - it is not
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on the global memory bus. */
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apic_io_memory = cpu_register_io_memory(apic_mem_read,
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apic_mem_write, NULL);
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/* XXX: what if the base changes? */
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cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE,
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apic_io_memory);
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}
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s->timer = qemu_new_timer(vm_clock, apic_timer, s);
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s = DO_UPCAST(APICState, busdev.qdev, dev);
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vmstate_register(s->idx, &vmstate_apic, s);
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qemu_register_reset(apic_reset, s);
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local_apics[s->idx] = s;
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return s;
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}
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static int apic_init1(SysBusDevice *dev)
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{
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APICState *s = FROM_SYSBUS(APICState, dev);
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int apic_io_memory;
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static int last_apic_idx;
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if (last_apic_idx >= MAX_APICS) {
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return -1;
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}
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apic_io_memory = cpu_register_io_memory(apic_mem_read,
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apic_mem_write, NULL);
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sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
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s->timer = qemu_new_timer(vm_clock, apic_timer, s);
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s->idx = last_apic_idx++;
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local_apics[s->idx] = s;
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return 0;
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}
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static SysBusDeviceInfo apic_info = {
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.init = apic_init1,
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.qdev.name = "apic",
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.qdev.size = sizeof(APICState),
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.qdev.vmsd = &vmstate_apic,
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.qdev.reset = apic_reset,
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.qdev.no_user = 1,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT8("id", APICState, id, -1),
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DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void apic_register_devices(void)
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{
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sysbus_register_withprop(&apic_info);
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}
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device_init(apic_register_devices)
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@ -7,7 +7,7 @@ void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode,
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uint8_t vector_num, uint8_t polarity,
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uint8_t trigger_mode);
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APICState *apic_init(CPUState *env, uint32_t apic_id);
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APICState *apic_init(void *env, uint8_t apic_id);
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int apic_accept_pic_intr(APICState *s);
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void apic_deliver_pic_intr(APICState *s, int level);
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int apic_get_interrupt(APICState *s);
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