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hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes

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As per "Loongson 3A5000/3B5000 Processor Reference Manual",
Loongson 3A5000's IPI implementation have 4 mailboxes per
core.

However, in 78464f023b ("hw/loongarch/virt: Modify ipi as
percpu device"), the number of IPI mailboxes was reduced to
one, which mismatches actual hardware.

It won't affect LoongArch based system as LoongArch boot code
only uses the first mailbox, however MIPS based Loongson boot
code uses all 4 mailboxes.

Fixes Coverity CID: 1512452, 1512453
Fixes: 78464f023b ("hw/loongarch/virt: Modify ipi as percpu device")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230521102307.87081-2-jiaxun.yang@flygoat.com>
Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Jiaxun Yang 2023-05-21 11:23:04 +01:00 committed by Song Gao
parent 848a6caa88
commit 8555ddc671
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
2 changed files with 6 additions and 4 deletions
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6
hw/intc/loongarch_ipi.c
View File

@ -238,14 +238,14 @@ static void loongarch_ipi_init(Object *obj)
static const VMStateDescription vmstate_ipi_core = {
.name = "ipi-single",
.version_id = 1,
.minimum_version_id = 1,
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(status, IPICore),
VMSTATE_UINT32(en, IPICore),
VMSTATE_UINT32(set, IPICore),
VMSTATE_UINT32(clear, IPICore),
VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
VMSTATE_END_OF_LIST()
}
};

4
include/hw/intc/loongarch_ipi.h
View File

@ -28,6 +28,8 @@
#define MAIL_SEND_OFFSET 0
#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
#define IPI_MBX_NUM 4
#define TYPE_LOONGARCH_IPI "loongarch_ipi"
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
@ -37,7 +39,7 @@ typedef struct IPICore {
uint32_t set;
uint32_t clear;
/* 64bit buf divide into 2 32bit buf */
uint32_t buf[2];
uint32_t buf[IPI_MBX_NUM * 2];
qemu_irq irq;
} IPICore;