target/riscv: add CPU QOM header
QMP CPU commands are usually implemented by a separated file, <arch>-qmp-cmds.c, to allow them to be build only for softmmu targets. This file uses a CPU QOM header with basic QOM declarations for the arch. We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch, but first we need a cpu-qom.h header with the definitions of TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from cpu.h to the new file, and cpu.h now includes "cpu-qom.h". Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230411183511.189632-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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/*
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* QEMU RISC-V CPU QOM header
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*
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* Copyright (c) 2023 Ventana Micro Systems Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_QOM_H
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#define RISCV_CPU_QOM_H
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#include "hw/core/cpu.h"
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#include "qom/object.h"
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#define TYPE_RISCV_CPU "riscv-cpu"
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#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
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#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
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#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
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#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
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#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
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#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
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#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
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#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
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#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
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#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
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#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
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#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
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#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
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#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
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#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
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#if defined(TARGET_RISCV32)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
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#elif defined(TARGET_RISCV64)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
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#endif
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typedef struct CPUArchState CPURISCVState;
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OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
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/**
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* RISCVCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_phases: The parent class' reset phase handlers.
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*
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* A RISCV CPU model.
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*/
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struct RISCVCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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};
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#endif /* RISCV_CPU_QOM_H */
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@ -28,6 +28,7 @@
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#include "qemu/int128.h"
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#include "qemu/int128.h"
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#include "cpu_bits.h"
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#include "cpu_bits.h"
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#include "qapi/qapi-types-common.h"
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#include "qapi/qapi-types-common.h"
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#include "cpu-qom.h"
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#define TCG_GUEST_DEFAULT_MO 0
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#define TCG_GUEST_DEFAULT_MO 0
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*/
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*/
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#define TARGET_INSN_START_EXTRA_WORDS 1
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#define TARGET_INSN_START_EXTRA_WORDS 1
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#define TYPE_RISCV_CPU "riscv-cpu"
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#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
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#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
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#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
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#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
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#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
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#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
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#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
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#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
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#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
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#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
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#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
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#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
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#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
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#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
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#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
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#if defined(TARGET_RISCV32)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
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#elif defined(TARGET_RISCV64)
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# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
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#endif
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#define RV(x) ((target_ulong)1 << (x - 'A'))
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#define RV(x) ((target_ulong)1 << (x - 'A'))
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/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
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/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */
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@ -109,8 +84,6 @@ typedef enum {
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#define MAX_RISCV_PMPS (16)
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#define MAX_RISCV_PMPS (16)
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typedef struct CPUArchState CPURISCVState;
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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#include "pmp.h"
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#include "pmp.h"
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#include "debug.h"
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#include "debug.h"
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@ -395,23 +368,6 @@ struct CPUArchState {
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uint64_t kvm_timer_frequency;
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uint64_t kvm_timer_frequency;
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};
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};
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OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
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/*
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* RISCVCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_phases: The parent class' reset phase handlers.
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*
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* A RISCV CPU model.
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*/
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struct RISCVCPUClass {
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/* < private > */
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CPUClass parent_class;
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/* < public > */
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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};
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/*
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/*
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* map is a 16-bit bitmap: the most significant set bit in map is the maximum
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* map is a 16-bit bitmap: the most significant set bit in map is the maximum
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* satp mode that is supported. It may be chosen by the user and must respect
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* satp mode that is supported. It may be chosen by the user and must respect
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