e1000: allow command-line selection of card model
Allow selection of different card models from the qemu command line, to better accomodate a wider range of guests. Signed-off-by: Romain Dolbeau <romain@dolbeau.org> Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Gabriel L. Somlo
Stefan Hajnoczi
parent
b44672849a
commit
8597f2e19e
120
hw/net/e1000.c
120
hw/net/e1000.c
@ -69,23 +69,13 @@ static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
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/*
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* HW models:
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* E1000_DEV_ID_82540EM works with Windows and Linux
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* E1000_DEV_ID_82540EM works with Windows, Linux, and OS X <= 10.8
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* E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
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* appears to perform better than 82540EM, but breaks with Linux 2.6.18
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* E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
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* E1000_DEV_ID_82545EM_COPPER works with Linux and OS X >= 10.6
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* Others never tested
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*/
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enum { E1000_DEVID = E1000_DEV_ID_82540EM };
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/*
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* May need to specify additional MAC-to-PHY entries --
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* Intel's Windows driver refuses to initialize unless they match
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*/
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enum {
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PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
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E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
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/* default to E1000_DEV_ID_82540EM */ 0xc20
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};
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typedef struct E1000State_st {
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/*< private >*/
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@ -151,10 +141,21 @@ typedef struct E1000State_st {
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uint32_t compat_flags;
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} E1000State;
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#define TYPE_E1000 "e1000"
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typedef struct E1000BaseClass {
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PCIDeviceClass parent_class;
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uint16_t phy_id2;
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bool is_8257xx;
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} E1000BaseClass;
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#define TYPE_E1000_BASE "e1000-base"
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#define E1000(obj) \
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OBJECT_CHECK(E1000State, (obj), TYPE_E1000)
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OBJECT_CHECK(E1000State, (obj), TYPE_E1000_BASE)
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#define E1000_DEVICE_CLASS(klass) \
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OBJECT_CLASS_CHECK(E1000BaseClass, (klass), TYPE_E1000_BASE)
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#define E1000_DEVICE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(E1000BaseClass, (obj), TYPE_E1000_BASE)
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#define defreg(x) x = (E1000_##x>>2)
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enum {
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@ -232,10 +233,11 @@ static const char phy_regcap[0x20] = {
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[PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
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};
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/* PHY_ID2 documented in 8254x_GBe_SDM.pdf, pp. 250 */
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static const uint16_t phy_reg_init[] = {
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[PHY_CTRL] = 0x1140,
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[PHY_STATUS] = 0x794d, /* link initially up with not completed autoneg */
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[PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
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[PHY_ID1] = 0x141, /* [PHY_ID2] configured per DevId, from e1000_reset() */
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[PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
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[M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
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[PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
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@ -269,13 +271,15 @@ static void
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set_interrupt_cause(E1000State *s, int index, uint32_t val)
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{
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PCIDevice *d = PCI_DEVICE(s);
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E1000BaseClass *edc = E1000_DEVICE_GET_CLASS(d);
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uint32_t pending_ints;
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uint32_t mit_delay;
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if (val && (E1000_DEVID >= E1000_DEV_ID_82547EI_MOBILE)) {
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/* Only for 8257x */
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if (val && edc->is_8257xx) {
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/* hack only for 8257xx models */
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val |= E1000_ICR_INT_ASSERTED;
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}
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s->mac_reg[ICR] = val;
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/*
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@ -375,6 +379,7 @@ rxbufsize(uint32_t v)
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static void e1000_reset(void *opaque)
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{
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E1000State *d = opaque;
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E1000BaseClass *edc = E1000_DEVICE_GET_CLASS(d);
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uint8_t *macaddr = d->conf.macaddr.a;
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int i;
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@ -385,6 +390,7 @@ static void e1000_reset(void *opaque)
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d->mit_ide = 0;
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memset(d->phy_reg, 0, sizeof d->phy_reg);
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memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
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d->phy_reg[PHY_ID2] = edc->phy_id2;
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memset(d->mac_reg, 0, sizeof d->mac_reg);
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memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
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d->rxbuf_min_shift = 1;
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@ -1440,9 +1446,13 @@ static const VMStateDescription vmstate_e1000 = {
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}
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};
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/*
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* EEPROM contents documented in Tables 5-2 and 5-3, pp. 98-102.
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* Note: A valid DevId will be inserted during pci_e1000_init().
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*/
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static const uint16_t e1000_eeprom_template[64] = {
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0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
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0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
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0x3000, 0x1000, 0x6403, 0 /*DevId*/, 0x8086, 0 /*DevId*/, 0x8086, 0x3040,
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0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
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0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
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0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
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@ -1507,6 +1517,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
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{
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DeviceState *dev = DEVICE(pci_dev);
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E1000State *d = E1000(pci_dev);
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PCIDeviceClass *pdc = PCI_DEVICE_GET_CLASS(pci_dev);
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uint8_t *pci_conf;
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uint16_t checksum = 0;
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int i;
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@ -1531,6 +1542,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
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macaddr = d->conf.macaddr.a;
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for (i = 0; i < 3; i++)
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d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
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d->eeprom_data[11] = d->eeprom_data[13] = pdc->device_id;
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for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
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checksum += d->eeprom_data[i];
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checksum = (uint16_t) EEPROM_SUM - checksum;
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@ -1564,17 +1576,29 @@ static Property e1000_properties[] = {
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DEFINE_PROP_END_OF_LIST(),
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};
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typedef struct E1000Info {
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const char *name;
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uint16_t device_id;
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uint8_t revision;
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uint16_t phy_id2;
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bool is_8257xx;
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} E1000Info;
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static void e1000_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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E1000BaseClass *e = E1000_DEVICE_CLASS(klass);
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const E1000Info *info = data;
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k->init = pci_e1000_init;
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k->exit = pci_e1000_uninit;
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k->romfile = "efi-e1000.rom";
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = E1000_DEVID;
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k->revision = 0x03;
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k->device_id = info->device_id;
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k->revision = info->revision;
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e->phy_id2 = info->phy_id2;
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e->is_8257xx = info->is_8257xx;
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k->class_id = PCI_CLASS_NETWORK_ETHERNET;
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set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
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dc->desc = "Intel Gigabit Ethernet";
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@ -1583,16 +1607,64 @@ static void e1000_class_init(ObjectClass *klass, void *data)
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dc->props = e1000_properties;
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}
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static const TypeInfo e1000_info = {
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.name = TYPE_E1000,
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static const TypeInfo e1000_base_info = {
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.name = TYPE_E1000_BASE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(E1000State),
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.class_init = e1000_class_init,
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.class_size = sizeof(E1000BaseClass),
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.abstract = true,
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};
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static const E1000Info e1000_devices[] = {
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{
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.name = "e1000-82540em",
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.device_id = E1000_DEV_ID_82540EM,
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.revision = 0x03,
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.phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT,
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},
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{
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.name = "e1000-82544gc",
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.device_id = E1000_DEV_ID_82544GC_COPPER,
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.revision = 0x03,
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.phy_id2 = E1000_PHY_ID2_82544x,
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},
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{
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.name = "e1000-82545em",
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.device_id = E1000_DEV_ID_82545EM_COPPER,
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.revision = 0x03,
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.phy_id2 = E1000_PHY_ID2_8254xx_DEFAULT,
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},
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{
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.name = "e1000-82573l",
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.device_id = E1000_DEV_ID_82573L,
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.revision = 0x03,
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.phy_id2 = E1000_PHY_ID2_82573x,
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.is_8257xx = true,
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},
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};
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static const TypeInfo e1000_default_info = {
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.name = "e1000",
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.parent = "e1000-82540em",
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};
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static void e1000_register_types(void)
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{
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type_register_static(&e1000_info);
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int i;
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type_register_static(&e1000_base_info);
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for (i = 0; i < ARRAY_SIZE(e1000_devices); i++) {
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const E1000Info *info = &e1000_devices[i];
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TypeInfo type_info = {};
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type_info.name = info->name;
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type_info.parent = TYPE_E1000_BASE;
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type_info.class_data = (void *)info;
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type_info.class_init = e1000_class_init;
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type_register(&type_info);
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}
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type_register_static(&e1000_default_info);
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}
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type_init(e1000_register_types)
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@ -99,6 +99,12 @@
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#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
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#define E1000_DEV_ID_ICH8_IGP_M 0x104D
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/* Device Specific Register Defaults */
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#define E1000_PHY_ID2_82541x 0x380
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#define E1000_PHY_ID2_82544x 0xC30
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#define E1000_PHY_ID2_8254xx_DEFAULT 0xC20 /* 82540x, 82545x, and 82546x */
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#define E1000_PHY_ID2_82573x 0xCC0
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/* Register Set. (82543, 82544)
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*
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* Registers are defined to be 32 bits and should be accessed as 32 bit values.
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