target/arm: Flush tlbs for E2&0 translation regime
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4174,8 +4174,12 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
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static int vae1_tlbmask(CPUARMState *env)
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{
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/* Since we exclude secure first, we may read HCR_EL2 directly. */
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if (arm_is_secure_below_el3(env)) {
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return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0;
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} else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
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== (HCR_E2H | HCR_TGE)) {
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return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0;
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} else {
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return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0;
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}
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@ -4219,6 +4223,12 @@ static int alle1_tlbmask(CPUARMState *env)
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}
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}
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static int e2_tlbmask(CPUARMState *env)
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{
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/* TODO: ARMv8.4-SecEL2 */
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return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2;
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}
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static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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@ -4231,10 +4241,10 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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CPUState *cs = CPU(cpu);
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CPUState *cs = env_cpu(env);
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int mask = e2_tlbmask(env);
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tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
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tlb_flush_by_mmuidx(cs, mask);
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}
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static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -4259,8 +4269,9 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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int mask = e2_tlbmask(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
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}
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static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -4278,11 +4289,11 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
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* Currently handles both VAE2 and VALE2, since we don't support
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* flush-last-level-only.
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*/
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ARMCPU *cpu = env_archcpu(env);
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CPUState *cs = CPU(cpu);
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CPUState *cs = env_cpu(env);
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int mask = e2_tlbmask(env);
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
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tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
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}
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static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
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