exec: Add both big- and little-endian memory helpers
Step three in the transition: helpers not tied to the target "default" endianness. To be used when the guest uses a memory operation with non-default endianness. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
f713d6ad7b
commit
867b3201a3
@ -70,6 +70,48 @@
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#define ADDR_READ addr_read
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#endif
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#if DATA_SIZE == 8
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# define BSWAP(X) bswap64(X)
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#elif DATA_SIZE == 4
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# define BSWAP(X) bswap32(X)
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#elif DATA_SIZE == 2
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# define BSWAP(X) bswap16(X)
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#else
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# define BSWAP(X) (X)
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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# define TGT_BE(X) (X)
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# define TGT_LE(X) BSWAP(X)
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#else
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# define TGT_BE(X) BSWAP(X)
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# define TGT_LE(X) (X)
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#endif
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#if DATA_SIZE == 1
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# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
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# define helper_be_ld_name helper_le_ld_name
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# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
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# define helper_be_lds_name helper_le_lds_name
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# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
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# define helper_be_st_name helper_le_st_name
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#else
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# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
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# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
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# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
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# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
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# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
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# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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# define helper_te_ld_name helper_be_ld_name
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# define helper_te_st_name helper_be_st_name
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#else
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# define helper_te_ld_name helper_le_ld_name
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# define helper_te_st_name helper_le_st_name
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#endif
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static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
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hwaddr physaddr,
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target_ulong addr,
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@ -89,18 +131,16 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
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return val;
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}
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/* handle all cases except unaligned access which span two pages */
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#ifdef SOFTMMU_CODE_ACCESS
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static
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static __attribute__((unused))
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#endif
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WORD_TYPE
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glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr, int mmu_idx,
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uintptr_t retaddr)
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WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
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uintptr_t retaddr)
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{
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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uintptr_t haddr;
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DATA_TYPE res;
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/* Adjust the given return address. */
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retaddr -= GETPC_ADJ;
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@ -124,7 +164,12 @@ glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)(CPUArchState *env,
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goto do_unaligned_access;
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}
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ioaddr = env->iotlb[mmu_idx][index];
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return glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
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res = TGT_LE(res);
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return res;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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@ -132,7 +177,7 @@ glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)(CPUArchState *env,
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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target_ulong addr1, addr2;
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DATA_TYPE res1, res2, res;
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DATA_TYPE res1, res2;
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unsigned shift;
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do_unaligned_access:
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#ifdef ALIGNED_ONLY
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@ -142,16 +187,12 @@ glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)(CPUArchState *env,
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addr2 = addr1 + DATA_SIZE;
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/* Note the adjustment at the beginning of the function.
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Undo that for the recursion. */
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res1 = glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
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(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
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res2 = glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
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(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
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res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
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res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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#ifdef TARGET_WORDS_BIGENDIAN
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res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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#else
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/* Little-endian combine. */
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res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
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#endif
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return res;
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}
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@ -163,16 +204,98 @@ glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)(CPUArchState *env,
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#endif
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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/* Note that ldl_raw is defined with type "int". */
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return (DATA_TYPE) glue(glue(ld, LSUFFIX), _raw)((uint8_t *)haddr);
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#if DATA_SIZE == 1
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res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
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#else
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res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
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#endif
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return res;
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}
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#if DATA_SIZE > 1
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#ifdef SOFTMMU_CODE_ACCESS
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static __attribute__((unused))
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#endif
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WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
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uintptr_t retaddr)
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{
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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uintptr_t haddr;
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DATA_TYPE res;
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/* Adjust the given return address. */
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retaddr -= GETPC_ADJ;
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/* If the TLB entry is for a different page, reload and try again. */
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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}
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#endif
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tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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hwaddr ioaddr;
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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ioaddr = env->iotlb[mmu_idx][index];
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
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res = TGT_BE(res);
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return res;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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target_ulong addr1, addr2;
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DATA_TYPE res1, res2;
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unsigned shift;
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do_unaligned_access:
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#ifdef ALIGNED_ONLY
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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#endif
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addr1 = addr & ~(DATA_SIZE - 1);
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addr2 = addr1 + DATA_SIZE;
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/* Note the adjustment at the beginning of the function.
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Undo that for the recursion. */
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res1 = helper_be_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
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res2 = helper_be_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
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shift = (addr & (DATA_SIZE - 1)) * 8;
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/* Big-endian combine. */
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res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
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return res;
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}
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/* Handle aligned access or unaligned access in the same page. */
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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}
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#endif
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
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return res;
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}
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#endif /* DATA_SIZE > 1 */
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DATA_TYPE
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glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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int mmu_idx)
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{
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return glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)(env, addr, mmu_idx,
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GETRA());
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return helper_te_ld_name (env, addr, mmu_idx, GETRA());
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}
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#ifndef SOFTMMU_CODE_ACCESS
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@ -180,14 +303,19 @@ glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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/* Provide signed versions of the load routines as well. We can of course
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avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
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#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
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WORD_TYPE
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glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr, int mmu_idx,
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uintptr_t retaddr)
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WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr)
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{
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return (SDATA_TYPE) glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
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(env, addr, mmu_idx, retaddr);
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return (SDATA_TYPE)helper_le_ld_name(env, addr, mmu_idx, retaddr);
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}
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# if DATA_SIZE > 1
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WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr)
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{
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return (SDATA_TYPE)helper_be_ld_name(env, addr, mmu_idx, retaddr);
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}
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# endif
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#endif
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static inline void glue(io_write, SUFFIX)(CPUArchState *env,
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@ -208,10 +336,8 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
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io_mem_write(mr, physaddr, val, 1 << SHIFT);
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}
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void
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glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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target_ulong addr, DATA_TYPE val,
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int mmu_idx, uintptr_t retaddr)
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void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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int mmu_idx, uintptr_t retaddr)
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{
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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@ -239,6 +365,10 @@ glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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goto do_unaligned_access;
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}
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ioaddr = env->iotlb[mmu_idx][index];
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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val = TGT_LE(val);
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glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
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return;
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}
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@ -256,11 +386,8 @@ glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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/* Note: relies on the fact that tlb_fill() does not remove the
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* previous page from the TLB cache. */
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for (i = DATA_SIZE - 1; i >= 0; i--) {
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#ifdef TARGET_WORDS_BIGENDIAN
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uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
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#else
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/* Little-endian extract. */
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uint8_t val8 = val >> (i * 8);
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#endif
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/* Note the adjustment at the beginning of the function.
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Undo that for the recursion. */
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glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
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@ -277,15 +404,91 @@ glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
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#endif
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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glue(glue(st, SUFFIX), _raw)((uint8_t *)haddr, val);
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#if DATA_SIZE == 1
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glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
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#else
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glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
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#endif
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}
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#if DATA_SIZE > 1
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void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
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int mmu_idx, uintptr_t retaddr)
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{
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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uintptr_t haddr;
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/* Adjust the given return address. */
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retaddr -= GETPC_ADJ;
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/* If the TLB entry is for a different page, reload and try again. */
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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}
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#endif
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tlb_fill(env, addr, 1, mmu_idx, retaddr);
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tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
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}
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/* Handle an IO access. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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hwaddr ioaddr;
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if ((addr & (DATA_SIZE - 1)) != 0) {
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goto do_unaligned_access;
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}
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ioaddr = env->iotlb[mmu_idx][index];
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/* ??? Note that the io helpers always read data in the target
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byte ordering. We should push the LE/BE request down into io. */
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val = TGT_BE(val);
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glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
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return;
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}
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/* Handle slow unaligned access (it spans two pages or IO). */
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if (DATA_SIZE > 1
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&& unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
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>= TARGET_PAGE_SIZE)) {
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int i;
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do_unaligned_access:
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#ifdef ALIGNED_ONLY
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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#endif
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/* XXX: not efficient, but simple */
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/* Note: relies on the fact that tlb_fill() does not remove the
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* previous page from the TLB cache. */
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for (i = DATA_SIZE - 1; i >= 0; i--) {
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/* Big-endian extract. */
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uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
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/* Note the adjustment at the beginning of the function.
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Undo that for the recursion. */
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glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
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mmu_idx, retaddr + GETPC_ADJ);
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}
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return;
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}
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/* Handle aligned access or unaligned access in the same page. */
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#ifdef ALIGNED_ONLY
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if ((addr & (DATA_SIZE - 1)) != 0) {
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do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
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}
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#endif
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
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}
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#endif /* DATA_SIZE > 1 */
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void
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glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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DATA_TYPE val, int mmu_idx)
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{
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glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, val, mmu_idx,
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GETRA());
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helper_te_st_name(env, addr, val, mmu_idx, GETRA());
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}
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#endif /* !defined(SOFTMMU_CODE_ACCESS) */
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@ -301,3 +504,16 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
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#undef SDATA_TYPE
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#undef USUFFIX
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#undef SSUFFIX
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#undef BSWAP
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#undef TGT_BE
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#undef TGT_LE
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#undef CPU_BE
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#undef CPU_LE
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#undef helper_le_ld_name
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#undef helper_be_ld_name
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#undef helper_le_lds_name
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#undef helper_be_lds_name
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#undef helper_le_st_name
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#undef helper_be_st_name
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#undef helper_te_ld_name
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#undef helper_te_st_name
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69
tcg/tcg.h
69
tcg/tcg.h
@ -774,29 +774,66 @@ void tcg_register_jit(void *buf, size_t buf_size);
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/* Value zero-extended to tcg register size. */
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tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_ret_lduw_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_ret_ldul_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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uint64_t helper_ret_ldq_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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/* Value sign-extended to tcg register size. */
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tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_ret_ldsw_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_ret_ldsl_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
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int mmu_idx, uintptr_t retaddr);
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void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
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int mmu_idx, uintptr_t retaddr);
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void helper_ret_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
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int mmu_idx, uintptr_t retaddr);
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void helper_ret_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void helper_ret_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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int mmu_idx, uintptr_t retaddr);
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void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
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int mmu_idx, uintptr_t retaddr);
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void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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int mmu_idx, uintptr_t retaddr);
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void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
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int mmu_idx, uintptr_t retaddr);
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void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
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int mmu_idx, uintptr_t retaddr);
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/* Temporary aliases until backends are converted. */
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#ifdef TARGET_WORDS_BIGENDIAN
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# define helper_ret_ldsw_mmu helper_be_ldsw_mmu
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# define helper_ret_lduw_mmu helper_be_lduw_mmu
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# define helper_ret_ldsl_mmu helper_be_ldsl_mmu
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# define helper_ret_ldul_mmu helper_be_ldul_mmu
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# define helper_ret_ldq_mmu helper_be_ldq_mmu
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# define helper_ret_stw_mmu helper_be_stw_mmu
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# define helper_ret_stl_mmu helper_be_stl_mmu
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# define helper_ret_stq_mmu helper_be_stq_mmu
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#else
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# define helper_ret_ldsw_mmu helper_le_ldsw_mmu
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# define helper_ret_lduw_mmu helper_le_lduw_mmu
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# define helper_ret_ldsl_mmu helper_le_ldsl_mmu
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# define helper_ret_ldul_mmu helper_le_ldul_mmu
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# define helper_ret_ldq_mmu helper_le_ldq_mmu
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# define helper_ret_stw_mmu helper_le_stw_mmu
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# define helper_ret_stl_mmu helper_le_stl_mmu
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# define helper_ret_stq_mmu helper_le_stq_mmu
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#endif
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uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint16_t helper_ldw_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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