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i8259: Clear ELCR on reset

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The ELCR is actually part of the chipset but we model it here for
simplicity reasons. The PIIX3 clears the ELCR on reset, which was once
broken by 4dbe19e181. Fix this by splitting up pic_init_reset from
pic_reset and clearing the register in the latter.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Jan Kiszka 2011-10-07 09:19:45 +02:00 committed by Blue Swirl
parent 51d9e939b8
commit 86fbf97ceb
1 changed files with 10 additions and 5 deletions
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15
hw/i8259.c
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@ -263,10 +263,8 @@ int pic_read_irq(PicState2 *s)
return intno; return intno;
} }
static void pic_reset(void *opaque) static void pic_init_reset(PicState *s)
{ {
PicState *s = opaque;
s->last_irr = 0; s->last_irr = 0;
s->irr = 0; s->irr = 0;
s->imr = 0; s->imr = 0;
@ -286,6 +284,14 @@ static void pic_reset(void *opaque)
pic_update_irq(s->pics_state); pic_update_irq(s->pics_state);
} }
static void pic_reset(void *opaque)
{
PicState *s = opaque;
pic_init_reset(s);
s->elcr = 0;
}
static void pic_ioport_write(void *opaque, target_phys_addr_t addr64, static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
uint64_t val64, unsigned size) uint64_t val64, unsigned size)
{ {
@ -297,8 +303,7 @@ static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val); DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
if (addr == 0) { if (addr == 0) {
if (val & 0x10) { if (val & 0x10) {
/* init */ pic_init_reset(s);
pic_reset(s);
s->init_state = 1; s->init_state = 1;
s->init4 = val & 1; s->init4 = val & 1;
s->single_mode = val & 2; s->single_mode = val & 2;