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target/tricore: Introduce priv tb flag 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-6-kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-06-21 16:22:59 +02:00
parent d8f466af7c
commit 878d1b6a90
2 changed files with 20 additions and 11 deletions
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17
target/tricore/cpu.h
View File

@ -263,10 +263,11 @@ void icr_set_ie(CPUTriCoreState *env, uint32_t val);
#define MASK_DBGSR_PEVT 0x40
#define MASK_DBGSR_EVTSRC 0x1f00
#define TRICORE_HFLAG_KUU 0x3
#define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
#define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
#define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */
enum tricore_priv_levels {
TRICORE_PRIV_UM0 = 0x0, /* user mode-0 flag */
TRICORE_PRIV_UM1 = 0x1, /* user mode-1 flag */
TRICORE_PRIV_SM = 0x2, /* kernel mode flag */
};
enum tricore_features {
TRICORE_FEATURE_13,
@ -378,15 +379,21 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, PRIV, 0, 2)
void cpu_state_reset(CPUTriCoreState *s);
void tricore_tcg_init(void);
static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
uint32_t new_flags = 0;
*pc = env->PC;
*cs_base = 0;
*flags = 0;
new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV,
extract32(env->PSW, 10, 2));
*flags = new_flags;
}
#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU

14
target/tricore/translate.c
View File

@ -76,7 +76,7 @@ typedef struct DisasContext {
uint32_t opcode;
/* Routine used to access memory */
int mem_idx;
uint32_t hflags, saved_hflags;
int priv;
uint64_t features;
uint32_t icr_ie_mask, icr_ie_offset;
} DisasContext;
@ -378,7 +378,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret, int32_t offset)
static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
int32_t offset)
{
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
if (ctx->priv == TRICORE_PRIV_SM) {
/* since we're caching PSW make this a special case */
if (offset == 0xfe04) {
gen_helper_psw_write(cpu_env, r1);
@ -7920,7 +7920,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
ctx->base.is_jmp = DISAS_EXIT;
break;
case OPC2_32_SYS_RFM:
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
if (ctx->priv == TRICORE_PRIV_SM) {
tmp = tcg_temp_new();
l1 = gen_new_label();
@ -7942,8 +7942,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
break;
case OPC2_32_SYS_RESTORE:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
(ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) {
tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
} /* else raise privilege trap */
} else {
@ -8313,7 +8312,10 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUTriCoreState *env = cs->env_ptr;
ctx->mem_idx = cpu_mmu_index(env, false);
ctx->hflags = (uint32_t)ctx->base.tb->flags;
uint32_t tb_flags = (uint32_t)ctx->base.tb->flags;
ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
ctx->features = env->features;
if (has_feature(ctx, TRICORE_FEATURE_161)) {
ctx->icr_ie_mask = R_ICR_IE_161_MASK;