target/arm: Vectorize USHL and SSHL
These instructions shift left or right depending on the sign of the input, and 7 bits are significant to the shift. This requires several masks and selects in addition to the actual shifts to form the complete answer. That said, the operation is still a small improvement even for two 64-bit elements -- 13 vector operations instead of 2 * 7 integer operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200216214232.4230-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
7abc8cabad
commit
87b74e8b6e
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@ -303,14 +303,8 @@ DEF_HELPER_2(neon_abd_s16, i32, i32, i32)
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DEF_HELPER_2(neon_abd_u32, i32, i32, i32)
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DEF_HELPER_2(neon_abd_s32, i32, i32, i32)
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DEF_HELPER_2(neon_shl_u8, i32, i32, i32)
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DEF_HELPER_2(neon_shl_s8, i32, i32, i32)
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DEF_HELPER_2(neon_shl_u16, i32, i32, i32)
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DEF_HELPER_2(neon_shl_s16, i32, i32, i32)
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DEF_HELPER_2(neon_shl_u32, i32, i32, i32)
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DEF_HELPER_2(neon_shl_s32, i32, i32, i32)
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DEF_HELPER_2(neon_shl_u64, i64, i64, i64)
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DEF_HELPER_2(neon_shl_s64, i64, i64, i64)
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DEF_HELPER_2(neon_rshl_u8, i32, i32, i32)
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DEF_HELPER_2(neon_rshl_s8, i32, i32, i32)
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DEF_HELPER_2(neon_rshl_u16, i32, i32, i32)
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@ -697,6 +691,11 @@ DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
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DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
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DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
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DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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#ifdef TARGET_AARCH64
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#include "helper-a64.h"
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#include "helper-sve.h"
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@ -615,24 +615,9 @@ NEON_VOP(abd_u32, neon_u32, 1)
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} else { \
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dest = src1 << tmp; \
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}} while (0)
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NEON_VOP(shl_u8, neon_u8, 4)
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NEON_VOP(shl_u16, neon_u16, 2)
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NEON_VOP(shl_u32, neon_u32, 1)
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#undef NEON_FN
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uint64_t HELPER(neon_shl_u64)(uint64_t val, uint64_t shiftop)
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{
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int8_t shift = (int8_t)shiftop;
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if (shift >= 64 || shift <= -64) {
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val = 0;
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} else if (shift < 0) {
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val >>= -shift;
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} else {
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val <<= shift;
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}
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return val;
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}
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#define NEON_FN(dest, src1, src2) do { \
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int8_t tmp; \
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tmp = (int8_t)src2; \
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@ -645,27 +630,9 @@ uint64_t HELPER(neon_shl_u64)(uint64_t val, uint64_t shiftop)
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} else { \
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dest = src1 << tmp; \
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}} while (0)
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NEON_VOP(shl_s8, neon_s8, 4)
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NEON_VOP(shl_s16, neon_s16, 2)
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NEON_VOP(shl_s32, neon_s32, 1)
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#undef NEON_FN
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uint64_t HELPER(neon_shl_s64)(uint64_t valop, uint64_t shiftop)
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{
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int8_t shift = (int8_t)shiftop;
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int64_t val = valop;
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if (shift >= 64) {
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val = 0;
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} else if (shift <= -64) {
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val >>= 63;
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} else if (shift < 0) {
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val >>= -shift;
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} else {
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val <<= shift;
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}
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return val;
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}
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#define NEON_FN(dest, src1, src2) do { \
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int8_t tmp; \
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tmp = (int8_t)src2; \
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@ -8744,9 +8744,9 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
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break;
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case 0x8: /* SSHL, USHL */
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if (u) {
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gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm);
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gen_ushl_i64(tcg_rd, tcg_rn, tcg_rm);
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} else {
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gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm);
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gen_sshl_i64(tcg_rd, tcg_rn, tcg_rm);
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}
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break;
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case 0x9: /* SQSHL, UQSHL */
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@ -11141,6 +11141,10 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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is_q ? 16 : 8, vec_full_reg_size(s),
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(u ? uqsub_op : sqsub_op) + size);
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return;
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case 0x08: /* SSHL, USHL */
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gen_gvec_op3(s, is_q, rd, rn, rm,
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u ? &ushl_op[size] : &sshl_op[size]);
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return;
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case 0x0c: /* SMAX, UMAX */
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if (u) {
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);
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@ -11256,16 +11260,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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genfn = fns[size][u];
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break;
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}
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case 0x8: /* SSHL, USHL */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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{ gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 },
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{ gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 },
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{ gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 },
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};
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genfn = fns[size][u];
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break;
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}
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case 0x9: /* SQSHL, UQSHL */
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{
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static NeonGenTwoOpEnvFn * const fns[3][2] = {
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@ -3575,13 +3575,13 @@ static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift,
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if (u) {
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switch (size) {
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case 1: gen_helper_neon_shl_u16(var, var, shift); break;
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case 2: gen_helper_neon_shl_u32(var, var, shift); break;
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case 2: gen_ushl_i32(var, var, shift); break;
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default: abort();
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}
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} else {
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switch (size) {
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case 1: gen_helper_neon_shl_s16(var, var, shift); break;
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case 2: gen_helper_neon_shl_s32(var, var, shift); break;
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case 2: gen_sshl_i32(var, var, shift); break;
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default: abort();
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}
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}
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@ -4384,6 +4384,280 @@ const GVecGen3 cmtst_op[4] = {
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.vece = MO_64 },
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};
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void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
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{
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TCGv_i32 lval = tcg_temp_new_i32();
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TCGv_i32 rval = tcg_temp_new_i32();
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TCGv_i32 lsh = tcg_temp_new_i32();
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TCGv_i32 rsh = tcg_temp_new_i32();
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TCGv_i32 zero = tcg_const_i32(0);
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TCGv_i32 max = tcg_const_i32(32);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_ext8s_i32(lsh, shift);
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tcg_gen_neg_i32(rsh, lsh);
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tcg_gen_shl_i32(lval, src, lsh);
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tcg_gen_shr_i32(rval, src, rsh);
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tcg_gen_movcond_i32(TCG_COND_LTU, dst, lsh, max, lval, zero);
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tcg_gen_movcond_i32(TCG_COND_LTU, dst, rsh, max, rval, dst);
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tcg_temp_free_i32(lval);
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tcg_temp_free_i32(rval);
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tcg_temp_free_i32(lsh);
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tcg_temp_free_i32(rsh);
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tcg_temp_free_i32(zero);
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tcg_temp_free_i32(max);
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}
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void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
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{
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TCGv_i64 lval = tcg_temp_new_i64();
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TCGv_i64 rval = tcg_temp_new_i64();
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TCGv_i64 lsh = tcg_temp_new_i64();
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TCGv_i64 rsh = tcg_temp_new_i64();
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TCGv_i64 zero = tcg_const_i64(0);
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TCGv_i64 max = tcg_const_i64(64);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_ext8s_i64(lsh, shift);
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tcg_gen_neg_i64(rsh, lsh);
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tcg_gen_shl_i64(lval, src, lsh);
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tcg_gen_shr_i64(rval, src, rsh);
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tcg_gen_movcond_i64(TCG_COND_LTU, dst, lsh, max, lval, zero);
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tcg_gen_movcond_i64(TCG_COND_LTU, dst, rsh, max, rval, dst);
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tcg_temp_free_i64(lval);
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tcg_temp_free_i64(rval);
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tcg_temp_free_i64(lsh);
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tcg_temp_free_i64(rsh);
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tcg_temp_free_i64(zero);
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tcg_temp_free_i64(max);
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}
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static void gen_ushl_vec(unsigned vece, TCGv_vec dst,
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TCGv_vec src, TCGv_vec shift)
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{
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TCGv_vec lval = tcg_temp_new_vec_matching(dst);
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TCGv_vec rval = tcg_temp_new_vec_matching(dst);
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TCGv_vec lsh = tcg_temp_new_vec_matching(dst);
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TCGv_vec rsh = tcg_temp_new_vec_matching(dst);
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TCGv_vec msk, max;
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tcg_gen_neg_vec(vece, rsh, shift);
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if (vece == MO_8) {
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tcg_gen_mov_vec(lsh, shift);
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} else {
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msk = tcg_temp_new_vec_matching(dst);
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tcg_gen_dupi_vec(vece, msk, 0xff);
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tcg_gen_and_vec(vece, lsh, shift, msk);
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tcg_gen_and_vec(vece, rsh, rsh, msk);
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tcg_temp_free_vec(msk);
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}
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_shlv_vec(vece, lval, src, lsh);
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tcg_gen_shrv_vec(vece, rval, src, rsh);
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max = tcg_temp_new_vec_matching(dst);
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tcg_gen_dupi_vec(vece, max, 8 << vece);
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/*
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* The choice of LT (signed) and GEU (unsigned) are biased toward
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* the instructions of the x86_64 host. For MO_8, the whole byte
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* is significant so we must use an unsigned compare; otherwise we
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* have already masked to a byte and so a signed compare works.
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* Other tcg hosts have a full set of comparisons and do not care.
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*/
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if (vece == MO_8) {
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tcg_gen_cmp_vec(TCG_COND_GEU, vece, lsh, lsh, max);
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tcg_gen_cmp_vec(TCG_COND_GEU, vece, rsh, rsh, max);
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tcg_gen_andc_vec(vece, lval, lval, lsh);
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tcg_gen_andc_vec(vece, rval, rval, rsh);
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} else {
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tcg_gen_cmp_vec(TCG_COND_LT, vece, lsh, lsh, max);
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tcg_gen_cmp_vec(TCG_COND_LT, vece, rsh, rsh, max);
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tcg_gen_and_vec(vece, lval, lval, lsh);
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tcg_gen_and_vec(vece, rval, rval, rsh);
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}
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tcg_gen_or_vec(vece, dst, lval, rval);
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tcg_temp_free_vec(max);
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tcg_temp_free_vec(lval);
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tcg_temp_free_vec(rval);
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tcg_temp_free_vec(lsh);
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tcg_temp_free_vec(rsh);
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}
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static const TCGOpcode ushl_list[] = {
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INDEX_op_neg_vec, INDEX_op_shlv_vec,
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INDEX_op_shrv_vec, INDEX_op_cmp_vec, 0
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};
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const GVecGen3 ushl_op[4] = {
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{ .fniv = gen_ushl_vec,
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.fno = gen_helper_gvec_ushl_b,
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.opt_opc = ushl_list,
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.vece = MO_8 },
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{ .fniv = gen_ushl_vec,
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.fno = gen_helper_gvec_ushl_h,
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.opt_opc = ushl_list,
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.vece = MO_16 },
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{ .fni4 = gen_ushl_i32,
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.fniv = gen_ushl_vec,
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.opt_opc = ushl_list,
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.vece = MO_32 },
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{ .fni8 = gen_ushl_i64,
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.fniv = gen_ushl_vec,
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.opt_opc = ushl_list,
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.vece = MO_64 },
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};
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void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift)
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{
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TCGv_i32 lval = tcg_temp_new_i32();
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TCGv_i32 rval = tcg_temp_new_i32();
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TCGv_i32 lsh = tcg_temp_new_i32();
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TCGv_i32 rsh = tcg_temp_new_i32();
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TCGv_i32 zero = tcg_const_i32(0);
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TCGv_i32 max = tcg_const_i32(31);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_ext8s_i32(lsh, shift);
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tcg_gen_neg_i32(rsh, lsh);
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tcg_gen_shl_i32(lval, src, lsh);
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tcg_gen_umin_i32(rsh, rsh, max);
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tcg_gen_sar_i32(rval, src, rsh);
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tcg_gen_movcond_i32(TCG_COND_LEU, lval, lsh, max, lval, zero);
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tcg_gen_movcond_i32(TCG_COND_LT, dst, lsh, zero, rval, lval);
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tcg_temp_free_i32(lval);
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tcg_temp_free_i32(rval);
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tcg_temp_free_i32(lsh);
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tcg_temp_free_i32(rsh);
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tcg_temp_free_i32(zero);
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tcg_temp_free_i32(max);
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}
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void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift)
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{
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TCGv_i64 lval = tcg_temp_new_i64();
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TCGv_i64 rval = tcg_temp_new_i64();
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TCGv_i64 lsh = tcg_temp_new_i64();
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TCGv_i64 rsh = tcg_temp_new_i64();
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TCGv_i64 zero = tcg_const_i64(0);
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TCGv_i64 max = tcg_const_i64(63);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
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* unspecified results, not undefined behaviour (i.e. no trap).
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* Discard out-of-range results after the fact.
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*/
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tcg_gen_ext8s_i64(lsh, shift);
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tcg_gen_neg_i64(rsh, lsh);
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tcg_gen_shl_i64(lval, src, lsh);
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tcg_gen_umin_i64(rsh, rsh, max);
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tcg_gen_sar_i64(rval, src, rsh);
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tcg_gen_movcond_i64(TCG_COND_LEU, lval, lsh, max, lval, zero);
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tcg_gen_movcond_i64(TCG_COND_LT, dst, lsh, zero, rval, lval);
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tcg_temp_free_i64(lval);
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tcg_temp_free_i64(rval);
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tcg_temp_free_i64(lsh);
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tcg_temp_free_i64(rsh);
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tcg_temp_free_i64(zero);
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tcg_temp_free_i64(max);
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}
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static void gen_sshl_vec(unsigned vece, TCGv_vec dst,
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TCGv_vec src, TCGv_vec shift)
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{
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TCGv_vec lval = tcg_temp_new_vec_matching(dst);
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TCGv_vec rval = tcg_temp_new_vec_matching(dst);
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TCGv_vec lsh = tcg_temp_new_vec_matching(dst);
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TCGv_vec rsh = tcg_temp_new_vec_matching(dst);
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TCGv_vec tmp = tcg_temp_new_vec_matching(dst);
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/*
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* Rely on the TCG guarantee that out of range shifts produce
|
||||
* unspecified results, not undefined behaviour (i.e. no trap).
|
||||
* Discard out-of-range results after the fact.
|
||||
*/
|
||||
tcg_gen_neg_vec(vece, rsh, shift);
|
||||
if (vece == MO_8) {
|
||||
tcg_gen_mov_vec(lsh, shift);
|
||||
} else {
|
||||
tcg_gen_dupi_vec(vece, tmp, 0xff);
|
||||
tcg_gen_and_vec(vece, lsh, shift, tmp);
|
||||
tcg_gen_and_vec(vece, rsh, rsh, tmp);
|
||||
}
|
||||
|
||||
/* Bound rsh so out of bound right shift gets -1. */
|
||||
tcg_gen_dupi_vec(vece, tmp, (8 << vece) - 1);
|
||||
tcg_gen_umin_vec(vece, rsh, rsh, tmp);
|
||||
tcg_gen_cmp_vec(TCG_COND_GT, vece, tmp, lsh, tmp);
|
||||
|
||||
tcg_gen_shlv_vec(vece, lval, src, lsh);
|
||||
tcg_gen_sarv_vec(vece, rval, src, rsh);
|
||||
|
||||
/* Select in-bound left shift. */
|
||||
tcg_gen_andc_vec(vece, lval, lval, tmp);
|
||||
|
||||
/* Select between left and right shift. */
|
||||
if (vece == MO_8) {
|
||||
tcg_gen_dupi_vec(vece, tmp, 0);
|
||||
tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, rval, lval);
|
||||
} else {
|
||||
tcg_gen_dupi_vec(vece, tmp, 0x80);
|
||||
tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, lval, rval);
|
||||
}
|
||||
|
||||
tcg_temp_free_vec(lval);
|
||||
tcg_temp_free_vec(rval);
|
||||
tcg_temp_free_vec(lsh);
|
||||
tcg_temp_free_vec(rsh);
|
||||
tcg_temp_free_vec(tmp);
|
||||
}
|
||||
|
||||
static const TCGOpcode sshl_list[] = {
|
||||
INDEX_op_neg_vec, INDEX_op_umin_vec, INDEX_op_shlv_vec,
|
||||
INDEX_op_sarv_vec, INDEX_op_cmp_vec, INDEX_op_cmpsel_vec, 0
|
||||
};
|
||||
|
||||
const GVecGen3 sshl_op[4] = {
|
||||
{ .fniv = gen_sshl_vec,
|
||||
.fno = gen_helper_gvec_sshl_b,
|
||||
.opt_opc = sshl_list,
|
||||
.vece = MO_8 },
|
||||
{ .fniv = gen_sshl_vec,
|
||||
.fno = gen_helper_gvec_sshl_h,
|
||||
.opt_opc = sshl_list,
|
||||
.vece = MO_16 },
|
||||
{ .fni4 = gen_sshl_i32,
|
||||
.fniv = gen_sshl_vec,
|
||||
.opt_opc = sshl_list,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = gen_sshl_i64,
|
||||
.fniv = gen_sshl_vec,
|
||||
.opt_opc = sshl_list,
|
||||
.vece = MO_64 },
|
||||
};
|
||||
|
||||
static void gen_uqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat,
|
||||
TCGv_vec a, TCGv_vec b)
|
||||
{
|
||||
|
|
@ -4787,6 +5061,12 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
|
|||
vec_size, vec_size);
|
||||
}
|
||||
return 0;
|
||||
|
||||
case NEON_3R_VSHL:
|
||||
/* Note the operation is vshl vd,vm,vn */
|
||||
tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
|
||||
u ? &ushl_op[size] : &sshl_op[size]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (size == 3) {
|
||||
|
|
@ -4795,13 +5075,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
|
|||
neon_load_reg64(cpu_V0, rn + pass);
|
||||
neon_load_reg64(cpu_V1, rm + pass);
|
||||
switch (op) {
|
||||
case NEON_3R_VSHL:
|
||||
if (u) {
|
||||
gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
|
||||
} else {
|
||||
gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
|
||||
}
|
||||
break;
|
||||
case NEON_3R_VQSHL:
|
||||
if (u) {
|
||||
gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
|
||||
|
|
@ -4836,7 +5109,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
|
|||
}
|
||||
pairwise = 0;
|
||||
switch (op) {
|
||||
case NEON_3R_VSHL:
|
||||
case NEON_3R_VQSHL:
|
||||
case NEON_3R_VRSHL:
|
||||
case NEON_3R_VQRSHL:
|
||||
|
|
@ -4916,9 +5188,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
|
|||
case NEON_3R_VHSUB:
|
||||
GEN_NEON_INTEGER_OP(hsub);
|
||||
break;
|
||||
case NEON_3R_VSHL:
|
||||
GEN_NEON_INTEGER_OP(shl);
|
||||
break;
|
||||
case NEON_3R_VQSHL:
|
||||
GEN_NEON_INTEGER_OP_ENV(qshl);
|
||||
break;
|
||||
|
|
@ -5327,9 +5596,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
|
|||
}
|
||||
} else {
|
||||
if (input_unsigned) {
|
||||
gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
|
||||
gen_ushl_i64(cpu_V0, in, tmp64);
|
||||
} else {
|
||||
gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
|
||||
gen_sshl_i64(cpu_V0, in, tmp64);
|
||||
}
|
||||
}
|
||||
tmp = tcg_temp_new_i32();
|
||||
|
|
|
|||
|
|
@ -278,6 +278,8 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8);
|
|||
extern const GVecGen3 mla_op[4];
|
||||
extern const GVecGen3 mls_op[4];
|
||||
extern const GVecGen3 cmtst_op[4];
|
||||
extern const GVecGen3 sshl_op[4];
|
||||
extern const GVecGen3 ushl_op[4];
|
||||
extern const GVecGen2i ssra_op[4];
|
||||
extern const GVecGen2i usra_op[4];
|
||||
extern const GVecGen2i sri_op[4];
|
||||
|
|
@ -287,6 +289,10 @@ extern const GVecGen4 sqadd_op[4];
|
|||
extern const GVecGen4 uqsub_op[4];
|
||||
extern const GVecGen4 sqsub_op[4];
|
||||
void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
|
||||
void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
|
||||
void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
|
||||
void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
|
||||
void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
|
||||
|
||||
/*
|
||||
* Forward to the isar_feature_* tests given a DisasContext pointer.
|
||||
|
|
|
|||
|
|
@ -1046,3 +1046,91 @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
|
|||
do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
|
||||
get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
|
||||
}
|
||||
|
||||
void HELPER(gvec_sshl_b)(void *vd, void *vn, void *vm, uint32_t desc)
|
||||
{
|
||||
intptr_t i, opr_sz = simd_oprsz(desc);
|
||||
int8_t *d = vd, *n = vn, *m = vm;
|
||||
|
||||
for (i = 0; i < opr_sz; ++i) {
|
||||
int8_t mm = m[i];
|
||||
int8_t nn = n[i];
|
||||
int8_t res = 0;
|
||||
if (mm >= 0) {
|
||||
if (mm < 8) {
|
||||
res = nn << mm;
|
||||
}
|
||||
} else {
|
||||
res = nn >> (mm > -8 ? -mm : 7);
|
||||
}
|
||||
d[i] = res;
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_sshl_h)(void *vd, void *vn, void *vm, uint32_t desc)
|
||||
{
|
||||
intptr_t i, opr_sz = simd_oprsz(desc);
|
||||
int16_t *d = vd, *n = vn, *m = vm;
|
||||
|
||||
for (i = 0; i < opr_sz / 2; ++i) {
|
||||
int8_t mm = m[i]; /* only 8 bits of shift are significant */
|
||||
int16_t nn = n[i];
|
||||
int16_t res = 0;
|
||||
if (mm >= 0) {
|
||||
if (mm < 16) {
|
||||
res = nn << mm;
|
||||
}
|
||||
} else {
|
||||
res = nn >> (mm > -16 ? -mm : 15);
|
||||
}
|
||||
d[i] = res;
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_ushl_b)(void *vd, void *vn, void *vm, uint32_t desc)
|
||||
{
|
||||
intptr_t i, opr_sz = simd_oprsz(desc);
|
||||
uint8_t *d = vd, *n = vn, *m = vm;
|
||||
|
||||
for (i = 0; i < opr_sz; ++i) {
|
||||
int8_t mm = m[i];
|
||||
uint8_t nn = n[i];
|
||||
uint8_t res = 0;
|
||||
if (mm >= 0) {
|
||||
if (mm < 8) {
|
||||
res = nn << mm;
|
||||
}
|
||||
} else {
|
||||
if (mm > -8) {
|
||||
res = nn >> -mm;
|
||||
}
|
||||
}
|
||||
d[i] = res;
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
||||
void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc)
|
||||
{
|
||||
intptr_t i, opr_sz = simd_oprsz(desc);
|
||||
uint16_t *d = vd, *n = vn, *m = vm;
|
||||
|
||||
for (i = 0; i < opr_sz / 2; ++i) {
|
||||
int8_t mm = m[i]; /* only 8 bits of shift are significant */
|
||||
uint16_t nn = n[i];
|
||||
uint16_t res = 0;
|
||||
if (mm >= 0) {
|
||||
if (mm < 16) {
|
||||
res = nn << mm;
|
||||
}
|
||||
} else {
|
||||
if (mm > -16) {
|
||||
res = nn >> -mm;
|
||||
}
|
||||
}
|
||||
d[i] = res;
|
||||
}
|
||||
clear_tail(d, opr_sz, simd_maxsz(desc));
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue