target/riscv: Implement SGEIP bit in hip and hie CSRs
A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-3-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -434,6 +434,7 @@ static void riscv_cpu_reset(DeviceState *dev)
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}
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}
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env->mcause = 0;
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env->miclaim = MIP_SGEIP;
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env->pc = env->resetvec;
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env->two_stage_lookup = false;
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/* mmte is supposed to have pm.current hardwired to 1 */
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@ -695,7 +696,7 @@ static void riscv_cpu_init(Object *obj)
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cpu_set_cpustate_pointers(cpu);
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#ifndef CONFIG_USER_ONLY
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qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
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qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
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#endif /* CONFIG_USER_ONLY */
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}
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@ -540,6 +540,8 @@ typedef enum RISCVException {
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#define IRQ_S_EXT 9
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#define IRQ_VS_EXT 10
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#define IRQ_M_EXT 11
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#define IRQ_S_GEXT 12
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#define IRQ_LOCAL_MAX 16
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/* mip masks */
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#define MIP_USIP (1 << IRQ_U_SOFT)
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@ -554,6 +556,7 @@ typedef enum RISCVException {
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#define MIP_SEIP (1 << IRQ_S_EXT)
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#define MIP_VSEIP (1 << IRQ_VS_EXT)
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#define MIP_MEIP (1 << IRQ_M_EXT)
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#define MIP_SGEIP (1 << IRQ_S_GEXT)
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/* sip masks */
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#define SIP_SSIP MIP_SSIP
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@ -461,12 +461,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
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#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
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#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
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#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
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#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
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static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
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VS_MODE_INTERRUPTS;
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static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
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static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
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VS_MODE_INTERRUPTS;
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HS_MODE_INTERRUPTS;
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#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
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(1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
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(1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
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@ -748,7 +749,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno,
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{
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env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
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if (riscv_has_ext(env, RVH)) {
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env->mideleg |= VS_MODE_INTERRUPTS;
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env->mideleg |= HS_MODE_INTERRUPTS;
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}
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return RISCV_EXCP_NONE;
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}
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@ -764,6 +765,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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env->mie = (env->mie & ~all_ints) | (val & all_ints);
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if (!riscv_has_ext(env, RVH)) {
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env->mie &= ~MIP_SGEIP;
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}
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return RISCV_EXCP_NONE;
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}
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@ -1110,7 +1114,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
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}
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if (ret_value) {
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*ret_value &= env->mideleg;
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*ret_value &= env->mideleg & S_MODE_INTERRUPTS;
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}
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return ret;
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}
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@ -1228,7 +1232,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
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write_mask & hvip_writable_mask);
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if (ret_value) {
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*ret_value &= hvip_writable_mask;
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*ret_value &= VS_MODE_INTERRUPTS;
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}
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return ret;
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}
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@ -1241,7 +1245,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
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write_mask & hip_writable_mask);
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if (ret_value) {
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*ret_value &= hip_writable_mask;
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*ret_value &= HS_MODE_INTERRUPTS;
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}
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return ret;
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}
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@ -1249,14 +1253,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
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static RISCVException read_hie(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->mie & VS_MODE_INTERRUPTS;
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*val = env->mie & HS_MODE_INTERRUPTS;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_hie(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
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target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
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return write_mie(env, CSR_MIE, newval);
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}
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