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cadence_ttc: Fix 'clear on read' behavior

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A missing call to qemu_set_irq() when reading the IRQ register
required SW to write to the IRQ register to acknowledge an
interrupt. With this patch the behavior is fixed:
 - Reading the interrupt register clears it and updates the timers
   interrupt status
 - Writes to the interrupt register are ignored

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Soren Brinkmann 2012-10-12 11:54:37 +01:00 committed by Peter Maydell
parent b4ae3cfa57
commit 884285bf64
1 changed files with 1 additions and 1 deletions
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2
hw/cadence_ttc.c
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@ -274,6 +274,7 @@ static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset)
/* cleared after read */ /* cleared after read */
value = s->reg_intr; value = s->reg_intr;
s->reg_intr = 0; s->reg_intr = 0;
cadence_timer_update(s);
return value; return value;
case 0x60: /* interrupt enable */ case 0x60: /* interrupt enable */
@ -355,7 +356,6 @@ static void cadence_ttc_write(void *opaque, target_phys_addr_t offset,
case 0x54: /* interrupt register */ case 0x54: /* interrupt register */
case 0x58: case 0x58:
case 0x5c: case 0x5c:
s->reg_intr &= (~value & 0xfff);
break; break;
case 0x60: /* interrupt enable */ case 0x60: /* interrupt enable */