OpenE2K/qemu-e2k
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target-arm queue:

Browse Source 
hw/arm/stm32f405: correctly describe the memory layout
  hw/arm: Add Olimex H405 board
  cubieboard: Support booting from an SD card image with u-boot on it
  target/arm: Fix sve_probe_page
  target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
  various code cleanups
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Merge tag 'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 hw/arm/stm32f405: correctly describe the memory layout
 hw/arm: Add Olimex H405 board
 cubieboard: Support booting from an SD card image with u-boot on it
 target/arm: Fix sve_probe_page
 target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
 various code cleanups

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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 13 Jan 2023 14:10:46 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm: (38 commits)
  target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
  hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock'
  hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'
  hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
  hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC
  hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
  hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE()
  hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name
  hw/arm/stellaris: Drop useless casts from void * to pointer
  hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name
  hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name
  hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name
  hw/arm/omap: Drop useless casts from void * to pointer
  hw/gpio/omap_gpio: Add local variable to avoid embedded cast
  hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState
  hw/arm: Remove unreachable code calling pflash_cfi01_register()
  hw/arm/vexpress: Remove dead code in vexpress_common_init()
  hw/arm/z2: Use the IEC binary prefix definitions
  hw/arm/omap_sx1: Use the IEC binary prefix definitions
  hw/arm/omap_sx1: Remove unused 'total_ram' definitions
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-01-13 14:12:43 +00:00
commit 886fb67020
76 changed files with 1951 additions and 455 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
MAINTAINERS
View File

@ -577,12 +577,14 @@ ARM Machines
Allwinner-a10
M: Beniamino Galvani <b.galvani@gmail.com>
M: Peter Maydell <peter.maydell@linaro.org>
R: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
L: qemu-arm@nongnu.org
S: Odd Fixes
F: hw/*/allwinner*
F: include/hw/*/allwinner*
F: hw/arm/cubieboard.c
F: docs/system/arm/cubieboard.rst
F: hw/misc/axp209.c
Allwinner-h3
M: Niek Linnenbank <nieklinnenbank@gmail.com>
@ -1036,6 +1038,12 @@ L: qemu-arm@nongnu.org
S: Maintained
F: hw/arm/netduinoplus2.c
Olimex STM32 H405
M: Felipe Balbi <balbi@kernel.org>
L: qemu-arm@nongnu.org
S: Maintained
F: hw/arm/olimex-stm32-h405.c
SmartFusion2
M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
M: Peter Maydell <peter.maydell@linaro.org>

1
configs/devices/arm-softmmu/default.mak
View File

@ -30,6 +30,7 @@ CONFIG_COLLIE=y
CONFIG_ASPEED_SOC=y
CONFIG_NETDUINO2=y
CONFIG_NETDUINOPLUS2=y
CONFIG_OLIMEX_STM32_H405=y
CONFIG_MPS2=y
CONFIG_RASPI=y
CONFIG_DIGIC=y

1
docs/system/arm/cubieboard.rst
View File

@ -14,3 +14,4 @@ Emulated devices:
- SDHCI
- USB controller
- SATA controller
- TWI (I2C) controller

1
docs/system/arm/orangepi.rst
View File

@ -25,6 +25,7 @@ The Orange Pi PC machine supports the following devices:
* Clock Control Unit
* System Control module
* Security Identifier device
* TWI (I2C)
Limitations
"""""""""""

1
docs/system/arm/stm32.rst
View File

@ -20,6 +20,7 @@ The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
compatible with STM32F2 series. The following machines are based on this chip :
- ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcontroller
- ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microcontroller
There are many other STM32 series that are currently not supported by QEMU.

9
hw/arm/Kconfig
View File

@ -119,6 +119,10 @@ config NETDUINOPLUS2
bool
select STM32F405_SOC
config OLIMEX_STM32_H405
bool
select STM32F405_SOC
config NSERIES
bool
select OMAP
@ -319,7 +323,11 @@ config ALLWINNER_A10
select AHCI
select ALLWINNER_A10_PIT
select ALLWINNER_A10_PIC
select ALLWINNER_A10_CCM
select ALLWINNER_A10_DRAMC
select ALLWINNER_EMAC
select ALLWINNER_I2C
select AXP209_PMU
select SERIAL
select UNIMP
@ -327,6 +335,7 @@ config ALLWINNER_H3
bool
select ALLWINNER_A10_PIT
select ALLWINNER_SUN8I_EMAC
select ALLWINNER_I2C
select SERIAL
select ARM_TIMER
select ARM_GIC

40
hw/arm/allwinner-a10.c
View File

@ -24,8 +24,12 @@
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/loader.h"
#define AW_A10_SRAM_A_BASE 0x00000000
#define AW_A10_DRAMC_BASE 0x01c01000
#define AW_A10_MMC0_BASE 0x01c0f000
#define AW_A10_CCM_BASE 0x01c20000
#define AW_A10_PIC_REG_BASE 0x01c20400
#define AW_A10_PIT_REG_BASE 0x01c20c00
#define AW_A10_UART0_REG_BASE 0x01c28000
@ -34,6 +38,23 @@
#define AW_A10_OHCI_BASE 0x01c14400
#define AW_A10_SATA_BASE 0x01c18000
#define AW_A10_RTC_BASE 0x01c20d00
#define AW_A10_I2C0_BASE 0x01c2ac00
void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
{
const int64_t rom_size = 32 * KiB;
g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
error_setg(&error_fatal, "%s: failed to read BlockBackend data",
__func__);
return;
}
rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
rom_size, AW_A10_SRAM_A_BASE,
NULL, NULL, NULL, NULL, false);
}
static void aw_a10_init(Object *obj)
{
@ -46,10 +67,16 @@ static void aw_a10_init(Object *obj)
object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
if (machine_usb(current_machine)) {
int i;
@ -103,6 +130,14 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
/* Clock Control Module */
sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
/* DRAM Control Module */
sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
@ -162,6 +197,11 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
/* RTC */
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
/* I2C */
sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
}
static void aw_a10_class_init(ObjectClass *oc, void *data)

11
hw/arm/allwinner-h3.c
View File

@ -53,6 +53,7 @@ const hwaddr allwinner_h3_memmap[] = {
[AW_H3_DEV_UART1] = 0x01c28400,
[AW_H3_DEV_UART2] = 0x01c28800,
[AW_H3_DEV_UART3] = 0x01c28c00,
[AW_H3_DEV_TWI0] = 0x01c2ac00,
[AW_H3_DEV_EMAC] = 0x01c30000,
[AW_H3_DEV_DRAMCOM] = 0x01c62000,
[AW_H3_DEV_DRAMCTL] = 0x01c63000,
@ -106,7 +107,6 @@ struct AwH3Unimplemented {
{ "uart1", 0x01c28400, 1 * KiB },
{ "uart2", 0x01c28800, 1 * KiB },
{ "uart3", 0x01c28c00, 1 * KiB },
{ "twi0", 0x01c2ac00, 1 * KiB },
{ "twi1", 0x01c2b000, 1 * KiB },
{ "twi2", 0x01c2b400, 1 * KiB },
{ "scr", 0x01c2c400, 1 * KiB },
@ -150,6 +150,7 @@ enum {
AW_H3_GIC_SPI_UART1 = 1,
AW_H3_GIC_SPI_UART2 = 2,
AW_H3_GIC_SPI_UART3 = 3,
AW_H3_GIC_SPI_TWI0 = 6,
AW_H3_GIC_SPI_TIMER0 = 18,
AW_H3_GIC_SPI_TIMER1 = 19,
AW_H3_GIC_SPI_MMC0 = 60,
@ -225,6 +226,8 @@ static void allwinner_h3_init(Object *obj)
"ram-size");
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
}
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@ -423,6 +426,12 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
/* I2C */
sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
/* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
create_unimplemented_device(unimplemented[i].device_name,

9
hw/arm/bcm2836.c
View File

@ -16,7 +16,7 @@
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
typedef struct BCM283XClass {
struct BCM283XClass {
/*< private >*/
DeviceClass parent_class;
/*< public >*/
@ -26,12 +26,7 @@ typedef struct BCM283XClass {
hwaddr peri_base; /* Peripheral base address seen by the CPU */
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
int clusterid;
} BCM283XClass;
#define BCM283X_CLASS(klass) \
OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
#define BCM283X_GET_CLASS(obj) \
OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
};
static Property bcm2836_enabled_cores_property =
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);

25
hw/arm/collie.c
View File

@ -20,6 +20,10 @@
#include "cpu.h"
#include "qom/object.h"
#define RAM_SIZE (512 * MiB)
#define FLASH_SIZE (32 * MiB)
#define FLASH_SECTOR_SIZE (64 * KiB)
struct CollieMachineState {
MachineState parent;
@ -31,12 +35,11 @@ OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE)
static struct arm_boot_info collie_binfo = {
.loader_start = SA_SDCS0,
.ram_size = 0x20000000,
.ram_size = RAM_SIZE,
};
static void collie_init(MachineState *machine)
{
DriveInfo *dinfo;
MachineClass *mc = MACHINE_GET_CLASS(machine);
CollieMachineState *cms = COLLIE_MACHINE(machine);
@ -51,15 +54,13 @@ static void collie_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
dinfo = drive_get(IF_PFLASH, 0, 1);
pflash_cfi01_register(SA_CS1, "collie.fl2", 0x02000000,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
for (unsigned i = 0; i < 2; i++) {
DriveInfo *dinfo = drive_get(IF_PFLASH, 0, i);
pflash_cfi01_register(i ? SA_CS1 : SA_CS0,
i ? "collie.fl2" : "collie.fl1", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
}
sysbus_create_simple("scoop", 0x40800000, NULL);
@ -75,7 +76,7 @@ static void collie_machine_class_init(ObjectClass *oc, void *data)
mc->init = collie_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
mc->default_ram_size = 0x20000000;
mc->default_ram_size = RAM_SIZE;
mc->default_ram_id = "strongarm.sdram";
}

11
hw/arm/cubieboard.c
View File

@ -20,6 +20,7 @@
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-a10.h"
#include "hw/i2c/i2c.h"
static struct arm_boot_info cubieboard_binfo = {
.loader_start = AW_A10_SDRAM_BASE,
@ -34,6 +35,7 @@ static void cubieboard_init(MachineState *machine)
BlockBackend *blk;
BusState *bus;
DeviceState *carddev;
I2CBus *i2c;
/* BIOS is not supported by this board */
if (machine->firmware) {
@ -80,6 +82,10 @@ static void cubieboard_init(MachineState *machine)
exit(1);
}
/* Connect AXP 209 */
i2c = I2C_BUS(qdev_get_child_bus(DEVICE(&a10->i2c0), "i2c"));
i2c_slave_create_simple(i2c, "axp209_pmu", 0x34);
/* Retrieve SD bus */
di = drive_get(IF_SD, 0, 0);
blk = di ? blk_by_legacy_dinfo(di) : NULL;
@ -93,6 +99,11 @@ static void cubieboard_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
machine->ram);
/* Load target kernel or start using BootROM */
if (!machine->kernel_filename && blk && blk_is_available(blk)) {
/* Use Boot ROM to copy data from SD card to SRAM */
allwinner_a10_bootrom_setup(a10, blk);
}
/* TODO create and connect IDE devices for ide_drive_get() */
cubieboard_binfo.ram_size = machine->ram_size;

45
hw/arm/gumstix.c
View File

@ -10,7 +10,7 @@
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
/*
* Example usage:
*
@ -35,6 +35,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "hw/arm/pxa.h"
#include "net/net.h"
@ -45,18 +46,20 @@
#include "sysemu/qtest.h"
#include "cpu.h"
static const int sector_len = 128 * 1024;
#define CONNEX_FLASH_SIZE (16 * MiB)
#define CONNEX_RAM_SIZE (64 * MiB)
#define VERDEX_FLASH_SIZE (32 * MiB)
#define VERDEX_RAM_SIZE (256 * MiB)
#define FLASH_SECTOR_SIZE (128 * KiB)
static void connex_init(MachineState *machine)
{
PXA2xxState *cpu;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
uint32_t connex_rom = 0x01000000;
uint32_t connex_ram = 0x04000000;
cpu = pxa255_init(address_space_mem, connex_ram);
cpu = pxa255_init(CONNEX_RAM_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!dinfo && !qtest_enabled()) {
@ -65,12 +68,10 @@ static void connex_init(MachineState *machine)
exit(1);
}
if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
sector_len, 2, 0, 0, 0, 0, 0)) {
error_report("Error registering flash memory");
exit(1);
}
/* Numonyx RC28F128J3F75 */
pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
/* Interrupt line of NIC is connected to GPIO line 36 */
smc91c111_init(&nd_table[0], 0x04000300,
@ -81,12 +82,8 @@ static void verdex_init(MachineState *machine)
{
PXA2xxState *cpu;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
uint32_t verdex_rom = 0x02000000;
uint32_t verdex_ram = 0x10000000;
cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);
cpu = pxa270_init(VERDEX_RAM_SIZE, machine->cpu_type);
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!dinfo && !qtest_enabled()) {
@ -95,12 +92,10 @@ static void verdex_init(MachineState *machine)
exit(1);
}
if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
sector_len, 2, 0, 0, 0, 0, 0)) {
error_report("Error registering flash memory");
exit(1);
}
/* Micron RC28F256P30TFA */
pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
/* Interrupt line of NIC is connected to GPIO line 99 */
smc91c111_init(&nd_table[0], 0x04000300,
@ -126,7 +121,7 @@ static void verdex_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Gumstix Verdex (PXA270)";
mc->desc = "Gumstix Verdex Pro XL6P COMs (PXA270)";
mc->init = verdex_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");

37
hw/arm/mainstone.c
View File

@ -12,6 +12,7 @@
* GNU GPL, version 2 or (at your option) any later version.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/arm/pxa.h"
@ -99,20 +100,20 @@ static const struct keymap map[0xE0] = {
enum mainstone_model_e { mainstone };
#define MAINSTONE_RAM 0x04000000
#define MAINSTONE_ROM 0x00800000
#define MAINSTONE_FLASH 0x02000000
#define MAINSTONE_RAM_SIZE (64 * MiB)
#define MAINSTONE_ROM_SIZE (8 * MiB)
#define MAINSTONE_FLASH_SIZE (32 * MiB)
static struct arm_boot_info mainstone_binfo = {
.loader_start = PXA2XX_SDRAM_BASE,
.ram_size = 0x04000000,
.ram_size = MAINSTONE_RAM_SIZE,
};
static void mainstone_common_init(MemoryRegion *address_space_mem,
MachineState *machine,
#define FLASH_SECTOR_SIZE (256 * KiB)
static void mainstone_common_init(MachineState *machine,
enum mainstone_model_e model, int arm_id)
{
uint32_t sector_len = 256 * 1024;
hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *mpu;
DeviceState *mst_irq;
@ -121,23 +122,19 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
MemoryRegion *rom = g_new(MemoryRegion, 1);
/* Setup CPU & memory */
mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
machine->cpu_type);
memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM_SIZE,
&error_fatal);
memory_region_add_subregion(address_space_mem, 0, rom);
memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
/* There are two 32MiB flash devices on the board */
for (i = 0; i < 2; i ++) {
dinfo = drive_get(IF_PFLASH, 0, i);
if (!pflash_cfi01_register(mainstone_flash_base[i],
i ? "mainstone.flash1" : "mainstone.flash0",
MAINSTONE_FLASH,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
sector_len, 4, 0, 0, 0, 0, 0)) {
error_report("Error registering flash memory");
exit(1);
}
pflash_cfi01_register(mainstone_flash_base[i],
i ? "mainstone.flash1" : "mainstone.flash0",
MAINSTONE_FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
}
mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
@ -165,7 +162,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
static void mainstone_init(MachineState *machine)
{
mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
mainstone_common_init(machine, mainstone, 0x196);
}
static void mainstone2_machine_init(MachineClass *mc)

1
hw/arm/meson.build
View File

@ -12,6 +12,7 @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))

9
hw/arm/musicpal.c
View File

@ -10,6 +10,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
@ -1196,6 +1197,8 @@ static const TypeInfo musicpal_key_info = {
.class_init = musicpal_key_class_init,
};
#define FLASH_SECTOR_SIZE (64 * KiB)
static struct arm_boot_info musicpal_binfo = {
.loader_start = 0x0,
.board_id = 0x20e,
@ -1264,8 +1267,8 @@ static void musicpal_init(MachineState *machine)
BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
flash_size = blk_getlength(blk);
if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
flash_size != 32*1024*1024) {
if (flash_size != 8 * MiB && flash_size != 16 * MiB &&
flash_size != 32 * MiB) {
error_report("Invalid flash image size");
exit(1);
}
@ -1277,7 +1280,7 @@ static void musicpal_init(MachineState *machine)
*/
pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX,
"musicpal.flash", flash_size,
blk, 0x10000,
blk, FLASH_SECTOR_SIZE,
MP_FLASH_SIZE_MAX / flash_size,
2, 0x00BF, 0x236D, 0x0000, 0x0000,
0x5555, 0x2AAA, 0);

69
hw/arm/olimex-stm32-h405.c Normal file
View File

@ -0,0 +1,69 @@
/*
* ST STM32VLDISCOVERY machine
* Olimex STM32-H405 machine
*
* Copyright (c) 2022 Felipe Balbi <balbi@kernel.org>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-clock.h"
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
/* Main SYSCLK frequency in Hz (168MHz) */
#define SYSCLK_FRQ 168000000ULL
static void olimex_stm32_h405_init(MachineState *machine)
{
DeviceState *dev;
Clock *sysclk;
/* This clock doesn't need migration because it is fixed-frequency */
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);
dev = qdev_new(TYPE_STM32F405_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu),
machine->kernel_filename,
0, FLASH_SIZE);
}
static void olimex_stm32_h405_machine_init(MachineClass *mc)
{
mc->desc = "Olimex STM32-H405 (Cortex-M4)";
mc->init = olimex_stm32_h405_init;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
/* SRAM pre-allocated as part of the SoC instantiation */
mc->default_ram_size = 0;
}
DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)

115
hw/arm/omap1.c
View File

@ -176,7 +176,7 @@ static void omap_timer_fire(void *opaque)
static void omap_timer_tick(void *opaque)
{
struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
struct omap_mpu_timer_s *timer = opaque;
omap_timer_sync(timer);
omap_timer_fire(timer);
@ -185,7 +185,7 @@ static void omap_timer_tick(void *opaque)
static void omap_timer_clk_update(void *opaque, int line, int on)
{
struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
struct omap_mpu_timer_s *timer = opaque;
omap_timer_sync(timer);
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
@ -202,7 +202,7 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
struct omap_mpu_timer_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@ -226,7 +226,7 @@ static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
static void omap_mpu_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
struct omap_mpu_timer_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@ -308,7 +308,7 @@ struct omap_watchdog_timer_s {
static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
struct omap_watchdog_timer_s *s = opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
@ -333,7 +333,7 @@ static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
static void omap_wd_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
struct omap_watchdog_timer_s *s = opaque;
if (size != 2) {
omap_badwidth_write16(opaque, addr, value);
@ -431,7 +431,7 @@ struct omap_32khz_timer_s {
static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
struct omap_32khz_timer_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
@ -458,7 +458,7 @@ static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
static void omap_os_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
struct omap_32khz_timer_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
@ -532,7 +532,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
uint16_t ret;
if (size != 2) {
@ -600,7 +600,7 @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
int64_t now, ticks;
int div, mult;
static const int bypass_div[4] = { 1, 2, 4, 4 };
@ -765,7 +765,7 @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@ -876,7 +876,7 @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
static void omap_pin_cfg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
uint32_t diff;
if (size != 4) {
@ -988,7 +988,7 @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
static uint64_t omap_id_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@ -1070,7 +1070,7 @@ static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@ -1103,7 +1103,7 @@ static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
static void omap_mpui_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@ -1168,7 +1168,7 @@ struct omap_tipb_bridge_s {
static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
struct omap_tipb_bridge_s *s = opaque;
if (size < 2) {
return omap_badwidth_read16(opaque, addr);
@ -1198,7 +1198,7 @@ static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
struct omap_tipb_bridge_s *s = opaque;
if (size < 2) {
omap_badwidth_write16(opaque, addr, value);
@ -1269,7 +1269,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
uint32_t ret;
if (size != 4) {
@ -1307,7 +1307,7 @@ static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
static void omap_tcmi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@ -1384,7 +1384,7 @@ struct dpll_ctl_s {
static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
struct dpll_ctl_s *s = opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
@ -1400,7 +1400,7 @@ static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
static void omap_dpll_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
struct dpll_ctl_s *s = opaque;
uint16_t diff;
static const int bypass_div[4] = { 1, 2, 4, 4 };
int div, mult;
@ -1464,7 +1464,7 @@ static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
@ -1668,7 +1668,7 @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
static void omap_clkm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
uint16_t diff;
omap_clk clk;
static const char *clkschemename[8] = {
@ -1756,7 +1756,7 @@ static const MemoryRegionOps omap_clkm_ops = {
static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
CPUState *cpu = CPU(s->cpu);
if (size != 2) {
@ -1801,7 +1801,7 @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
static void omap_clkdsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
uint16_t diff;
if (size != 2) {
@ -1911,7 +1911,7 @@ struct omap_mpuio_s {
static void omap_mpuio_set(void *opaque, int line, int level)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
struct omap_mpuio_s *s = opaque;
uint16_t prev = s->inputs;
if (level)
@ -1947,7 +1947,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
struct omap_mpuio_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
@ -2007,7 +2007,7 @@ static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
static void omap_mpuio_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
struct omap_mpuio_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
@ -2104,7 +2104,7 @@ static void omap_mpuio_reset(struct omap_mpuio_s *s)
static void omap_mpuio_onoff(void *opaque, int line, int on)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
struct omap_mpuio_s *s = opaque;
s->clk = on;
if (on)
@ -2198,10 +2198,9 @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
}
}
static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
struct omap_uwire_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
@ -2235,7 +2234,7 @@ static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
static void omap_uwire_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
struct omap_uwire_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
@ -2351,10 +2350,9 @@ static void omap_pwl_update(struct omap_pwl_s *s)
}
}
static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
struct omap_pwl_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@ -2374,7 +2372,7 @@ static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
static void omap_pwl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
struct omap_pwl_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@ -2414,7 +2412,7 @@ static void omap_pwl_reset(struct omap_pwl_s *s)
static void omap_pwl_clk_update(void *opaque, int line, int on)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
struct omap_pwl_s *s = opaque;
s->clk = on;
omap_pwl_update(s);
@ -2445,10 +2443,9 @@ struct omap_pwt_s {
omap_clk clk;
};
static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
struct omap_pwt_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@ -2470,7 +2467,7 @@ static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
static void omap_pwt_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
struct omap_pwt_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@ -2577,10 +2574,9 @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s)
printf("%s: conversion failed\n", __func__);
}
static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
struct omap_rtc_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint8_t i;
@ -2662,7 +2658,7 @@ static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
static void omap_rtc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
struct omap_rtc_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
struct tm new_tm;
time_t ti[2];
@ -3034,7 +3030,7 @@ static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
static void omap_mcbsp_source_tick(void *opaque)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
struct omap_mcbsp_s *s = opaque;
static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
if (!s->rx_rate)
@ -3080,7 +3076,7 @@ static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
static void omap_mcbsp_sink_tick(void *opaque)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
struct omap_mcbsp_s *s = opaque;
static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
if (!s->tx_rate)
@ -3173,7 +3169,7 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
@ -3271,7 +3267,7 @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
@ -3407,7 +3403,7 @@ static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
static void omap_mcbsp_writew(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
struct omap_mcbsp_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (offset == 0x04) { /* DXR */
@ -3498,7 +3494,7 @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
struct omap_mcbsp_s *s = opaque;
if (s->rx_rate) {
s->rx_req = s->codec->in.len;
@ -3508,7 +3504,7 @@ static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
struct omap_mcbsp_s *s = opaque;
if (s->tx_rate) {
s->tx_req = s->codec->out.size;
@ -3590,10 +3586,9 @@ static void omap_lpg_reset(struct omap_lpg_s *s)
omap_lpg_update(s);
}
static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
struct omap_lpg_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@ -3615,7 +3610,7 @@ static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
static void omap_lpg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
struct omap_lpg_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
@ -3650,7 +3645,7 @@ static const MemoryRegionOps omap_lpg_ops = {
static void omap_lpg_clk_update(void *opaque, int line, int on)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
struct omap_lpg_s *s = opaque;
s->clk = on;
omap_lpg_update(s);
@ -3713,7 +3708,7 @@ static void omap_setup_mpui_io(MemoryRegion *system_memory,
/* General chip reset */
static void omap1_mpu_reset(void *opaque)
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *mpu = opaque;
omap_dma_reset(mpu->dma);
omap_mpu_timer_reset(mpu->timer[0]);
@ -3793,7 +3788,7 @@ static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
void omap_mpu_wakeup(void *opaque, int irq, int req)
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *mpu = opaque;
CPUState *cpu = CPU(mpu->cpu);
if (cpu->halted) {

40
hw/arm/omap2.c
View File

@ -167,7 +167,7 @@ static inline void omap_eac_out_empty(struct omap_eac_s *s)
static void omap_eac_in_cb(void *opaque, int avail_b)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
struct omap_eac_s *s = opaque;
s->codec.rxavail = avail_b >> 2;
omap_eac_in_refill(s);
@ -177,7 +177,7 @@ static void omap_eac_in_cb(void *opaque, int avail_b)
static void omap_eac_out_cb(void *opaque, int free_b)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
struct omap_eac_s *s = opaque;
s->codec.txavail = free_b >> 2;
if (s->codec.txlen)
@ -333,10 +333,9 @@ static void omap_eac_reset(struct omap_eac_s *s)
omap_eac_interrupt_update(s);
}
static uint64_t omap_eac_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_eac_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
struct omap_eac_s *s = opaque;
uint32_t ret;
if (size != 2) {
@ -452,7 +451,7 @@ static uint64_t omap_eac_read(void *opaque, hwaddr addr,
static void omap_eac_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
struct omap_eac_s *s = opaque;
if (size != 2) {
omap_badwidth_write16(opaque, addr, value);
@ -656,7 +655,7 @@ static void omap_sti_reset(struct omap_sti_s *s)
static uint64_t omap_sti_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
struct omap_sti_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@ -697,7 +696,7 @@ static uint64_t omap_sti_read(void *opaque, hwaddr addr,
static void omap_sti_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
struct omap_sti_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@ -751,8 +750,7 @@ static const MemoryRegionOps omap_sti_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, unsigned size)
{
OMAP_BAD_REG(addr);
return 0;
@ -761,7 +759,7 @@ static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
static void omap_sti_fifo_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
struct omap_sti_s *s = opaque;
int ch = addr >> 6;
uint8_t byte = value;
@ -1057,7 +1055,7 @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
struct omap_prcm_s *s = opaque;
uint32_t ret;
if (size != 4) {
@ -1369,7 +1367,7 @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
static void omap_prcm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
struct omap_prcm_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@ -1849,7 +1847,7 @@ struct omap_sysctl_s {
static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
struct omap_sysctl_s *s = opaque;
int pad_offset, byte_offset;
int value;
@ -1873,7 +1871,7 @@ static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
struct omap_sysctl_s *s = opaque;
switch (addr) {
case 0x000: /* CONTROL_REVISION */
@ -1971,10 +1969,9 @@ static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
return 0;
}
static void omap_sysctl_write8(void *opaque, hwaddr addr,
uint32_t value)
static void omap_sysctl_write8(void *opaque, hwaddr addr, uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
struct omap_sysctl_s *s = opaque;
int pad_offset, byte_offset;
int prev_value;
@ -1995,10 +1992,9 @@ static void omap_sysctl_write8(void *opaque, hwaddr addr,
}
}
static void omap_sysctl_write(void *opaque, hwaddr addr,
uint32_t value)
static void omap_sysctl_write(void *opaque, hwaddr addr, uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
struct omap_sysctl_s *s = opaque;
switch (addr) {
case 0x000: /* CONTROL_REVISION */
@ -2233,7 +2229,7 @@ static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
/* General chip reset */
static void omap2_mpu_reset(void *opaque)
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *mpu = opaque;
omap_dma_reset(mpu->dma);
omap_prcm_reset(mpu->prcm);

53
hw/arm/omap_sx1.c
View File

@ -26,6 +26,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "ui/console.h"
#include "hw/arm/omap.h"
@ -65,7 +66,7 @@
static uint64_t static_read(void *opaque, hwaddr offset,
unsigned size)
{
uint32_t *val = (uint32_t *) opaque;
uint32_t *val = opaque;
uint32_t mask = (4 / size) - 1;
return *val >> ((offset & mask) << 3);
@ -86,17 +87,15 @@ static const MemoryRegionOps static_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
#define sdram_size 0x02000000
#define sector_size (128 * 1024)
#define flash0_size (16 * 1024 * 1024)
#define flash1_size ( 8 * 1024 * 1024)
#define flash2_size (32 * 1024 * 1024)
#define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
#define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
#define SDRAM_SIZE (32 * MiB)
#define SECTOR_SIZE (128 * KiB)
#define FLASH0_SIZE (16 * MiB)
#define FLASH1_SIZE (8 * MiB)
#define FLASH2_SIZE (32 * MiB)
static struct arm_boot_info sx1_binfo = {
.loader_start = OMAP_EMIFF_BASE,
.ram_size = sdram_size,
.ram_size = SDRAM_SIZE,
.board_id = 0x265,
};
@ -113,7 +112,7 @@ static void sx1_init(MachineState *machine, const int version)
static uint32_t cs3val = 0x00001139;
DriveInfo *dinfo;
int fl_idx;
uint32_t flash_size = flash0_size;
uint32_t flash_size = FLASH0_SIZE;
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
@ -123,7 +122,7 @@ static void sx1_init(MachineState *machine, const int version)
}
if (version == 2) {
flash_size = flash2_size;
flash_size = FLASH2_SIZE;
}
memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram);
@ -153,13 +152,10 @@ static void sx1_init(MachineState *machine, const int version)
fl_idx = 0;
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
if (!pflash_cfi01_register(OMAP_CS0_BASE,
"omap_sx1.flash0-1", flash_size,
blk_by_legacy_dinfo(dinfo),
sector_size, 4, 0, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx);
}
pflash_cfi01_register(OMAP_CS0_BASE,
"omap_sx1.flash0-1", flash_size,
blk_by_legacy_dinfo(dinfo),
SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
fl_idx++;
}
@ -167,21 +163,18 @@ static void sx1_init(MachineState *machine, const int version)
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0",
flash1_size, &error_fatal);
FLASH1_SIZE, &error_fatal);
memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
"sx1.cs1", OMAP_CS1_SIZE - flash1_size);
"sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE);
memory_region_add_subregion(address_space,
OMAP_CS1_BASE + flash1_size, &cs[1]);
OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
if (!pflash_cfi01_register(OMAP_CS1_BASE,
"omap_sx1.flash1-1", flash1_size,
blk_by_legacy_dinfo(dinfo),
sector_size, 4, 0, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx);
}
pflash_cfi01_register(OMAP_CS1_BASE,
"omap_sx1.flash1-1", FLASH1_SIZE,
blk_by_legacy_dinfo(dinfo),
SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
fl_idx++;
} else {
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
@ -220,7 +213,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
mc->init = sx1_init_v2;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
mc->default_ram_size = sdram_size;
mc->default_ram_size = SDRAM_SIZE;
mc->default_ram_id = "omap1.dram";
}
@ -238,7 +231,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
mc->init = sx1_init_v1;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
mc->default_ram_size = sdram_size;
mc->default_ram_size = SDRAM_SIZE;
mc->default_ram_id = "omap1.dram";
}

2
hw/arm/palm.c
View File

@ -115,7 +115,7 @@ static struct {
static void palmte_button_event(void *opaque, int keycode)
{
struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *cpu = opaque;
if (palmte_keymap[keycode & 0x7f].row != -1)
omap_mpuio_key(cpu->mpuio,

8
hw/arm/pxa2xx.c
View File

@ -11,6 +11,7 @@
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qapi/error.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
@ -2091,9 +2092,9 @@ static void pxa2xx_reset(void *opaque, int line, int level)
}
/* Initialise a PXA270 integrated chip (ARM based core). */
PXA2xxState *pxa270_init(MemoryRegion *address_space,
unsigned int sdram_size, const char *cpu_type)
PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type)
{
MemoryRegion *address_space = get_system_memory();
PXA2xxState *s;
int i;
DriveInfo *dinfo;
@ -2230,8 +2231,9 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
}
/* Initialise a PXA255 integrated chip (ARM based core). */
PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
PXA2xxState *pxa255_init(unsigned int sdram_size)
{
MemoryRegion *address_space = get_system_memory();
PXA2xxState *s;
int i;
DriveInfo *dinfo;

6
hw/arm/spitz.c
View File

@ -986,18 +986,16 @@ static void spitz_common_init(MachineState *machine)
SpitzMachineState *sms = SPITZ_MACHINE(machine);
enum spitz_model_e model = smc->model;
PXA2xxState *mpu;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *rom = g_new(MemoryRegion, 1);
/* Setup CPU & memory */
mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
machine->cpu_type);
mpu = pxa270_init(spitz_binfo.ram_size, machine->cpu_type);
sms->mpu = mpu;
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
memory_region_init_rom(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
memory_region_add_subregion(address_space_mem, 0, rom);
memory_region_add_subregion(get_system_memory(), 0, rom);
/* Setup peripherals */
spitz_keyboard_register(mpu);

73
hw/arm/stellaris.c
View File

@ -674,9 +674,8 @@ static void stellaris_i2c_init(Object *obj)
#define STELLARIS_ADC_FIFO_FULL 0x1000
#define TYPE_STELLARIS_ADC "stellaris-adc"
typedef struct StellarisADCState stellaris_adc_state;
DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
TYPE_STELLARIS_ADC)
typedef struct StellarisADCState StellarisADCState;
DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC)
struct StellarisADCState {
SysBusDevice parent_obj;
@ -700,7 +699,7 @@ struct StellarisADCState {
qemu_irq irq[4];
};
static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n)
{
int tail;
@ -716,7 +715,7 @@ static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
return s->fifo[n].data[tail];
}
static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
static void stellaris_adc_fifo_write(StellarisADCState *s, int n,
uint32_t value)
{
int head;
@ -736,7 +735,7 @@ static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
}
static void stellaris_adc_update(stellaris_adc_state *s)
static void stellaris_adc_update(StellarisADCState *s)
{
int level;
int n;
@ -749,7 +748,7 @@ static void stellaris_adc_update(stellaris_adc_state *s)
static void stellaris_adc_trigger(void *opaque, int irq, int level)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
StellarisADCState *s = opaque;
int n;
for (n = 0; n < 4; n++) {
@ -771,7 +770,7 @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
}
}
static void stellaris_adc_reset(stellaris_adc_state *s)
static void stellaris_adc_reset(StellarisADCState *s)
{
int n;
@ -785,7 +784,7 @@ static void stellaris_adc_reset(stellaris_adc_state *s)
static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
StellarisADCState *s = opaque;
/* TODO: Implement this. */
if (offset >= 0x40 && offset < 0xc0) {
@ -833,7 +832,7 @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
static void stellaris_adc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
StellarisADCState *s = opaque;
/* TODO: Implement this. */
if (offset >= 0x40 && offset < 0xc0) {
@ -901,31 +900,31 @@ static const VMStateDescription vmstate_stellaris_adc = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(actss, stellaris_adc_state),
VMSTATE_UINT32(ris, stellaris_adc_state),
VMSTATE_UINT32(im, stellaris_adc_state),
VMSTATE_UINT32(emux, stellaris_adc_state),
VMSTATE_UINT32(ostat, stellaris_adc_state),
VMSTATE_UINT32(ustat, stellaris_adc_state),
VMSTATE_UINT32(sspri, stellaris_adc_state),
VMSTATE_UINT32(sac, stellaris_adc_state),
VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
VMSTATE_UINT32(noise, stellaris_adc_state),
VMSTATE_UINT32(actss, StellarisADCState),
VMSTATE_UINT32(ris, StellarisADCState),
VMSTATE_UINT32(im, StellarisADCState),
VMSTATE_UINT32(emux, StellarisADCState),
VMSTATE_UINT32(ostat, StellarisADCState),
VMSTATE_UINT32(ustat, StellarisADCState),
VMSTATE_UINT32(sspri, StellarisADCState),
VMSTATE_UINT32(sac, StellarisADCState),
VMSTATE_UINT32(fifo[0].state, StellarisADCState),
VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16),
VMSTATE_UINT32(ssmux[0], StellarisADCState),
VMSTATE_UINT32(ssctl[0], StellarisADCState),
VMSTATE_UINT32(fifo[1].state, StellarisADCState),
VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16),
VMSTATE_UINT32(ssmux[1], StellarisADCState),
VMSTATE_UINT32(ssctl[1], StellarisADCState),
VMSTATE_UINT32(fifo[2].state, StellarisADCState),
VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16),
VMSTATE_UINT32(ssmux[2], StellarisADCState),
VMSTATE_UINT32(ssctl[2], StellarisADCState),
VMSTATE_UINT32(fifo[3].state, StellarisADCState),
VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16),
VMSTATE_UINT32(ssmux[3], StellarisADCState),
VMSTATE_UINT32(ssctl[3], StellarisADCState),
VMSTATE_UINT32(noise, StellarisADCState),
VMSTATE_END_OF_LIST()
}
};
@ -933,7 +932,7 @@ static const VMStateDescription vmstate_stellaris_adc = {
static void stellaris_adc_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
stellaris_adc_state *s = STELLARIS_ADC(obj);
StellarisADCState *s = STELLARIS_ADC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
int n;
@ -1381,7 +1380,7 @@ static void stellaris_adc_class_init(ObjectClass *klass, void *data)
static const TypeInfo stellaris_adc_info = {
.name = TYPE_STELLARIS_ADC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(stellaris_adc_state),
.instance_size = sizeof(StellarisADCState),
.instance_init = stellaris_adc_init,
.class_init = stellaris_adc_class_init,
};

8
hw/arm/stm32f405_soc.c
View File

@ -139,6 +139,14 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
}
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE,
&err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm);
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);

2
hw/arm/tosa.c
View File

@ -242,7 +242,7 @@ static void tosa_init(MachineState *machine)
TC6393xbState *tmio;
DeviceState *scp0, *scp1;
mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
mpu = pxa255_init(tosa_binfo.ram_size);
memory_region_init_rom(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
memory_region_add_subregion(address_space_mem, 0, rom);

6
hw/arm/versatilepb.c
View File

@ -385,13 +385,11 @@ static void versatile_init(MachineState *machine, int board_id)
/* 0x34000000 NOR Flash */
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
VERSATILE_FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
VERSATILE_FLASH_SECT_SIZE,
4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
}
4, 0x0089, 0x0018, 0x0000, 0x0, 0);
versatile_binfo.ram_size = machine->ram_size;
versatile_binfo.board_id = board_id;

10
hw/arm/vexpress.c
View File

@ -659,10 +659,6 @@ static void vexpress_common_init(MachineState *machine)
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
dinfo);
if (!pflash0) {
error_report("vexpress: error registering flash 0");
exit(1);
}
if (map[VE_NORFLASHALIAS] != -1) {
/* Map flash 0 as an alias into low memory */
@ -673,11 +669,7 @@ static void vexpress_common_init(MachineState *machine)
}
dinfo = drive_get(IF_PFLASH, 0, 1);
if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
dinfo)) {
error_report("vexpress: error registering flash 1");
exit(1);
}
ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo);
sram_size = 0x2000000;
memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,

16
hw/arm/z2.c
View File

@ -12,6 +12,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/arm/pxa.h"
#include "hw/arm/boot.h"
#include "hw/i2c/i2c.h"
@ -297,10 +298,10 @@ static const TypeInfo aer915_info = {
.class_init = aer915_class_init,
};
#define FLASH_SECTOR_SIZE (64 * KiB)
static void z2_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
uint32_t sector_len = 0x10000;
PXA2xxState *mpu;
DriveInfo *dinfo;
void *z2_lcd;
@ -308,15 +309,12 @@ static void z2_init(MachineState *machine)
DeviceState *wm;
/* Setup CPU & memory */
mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);
mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
dinfo = drive_get(IF_PFLASH, 0, 0);
if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
sector_len, 4, 0, 0, 0, 0, 0)) {
error_report("Error registering flash memory");
exit(1);
}
pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
/* setup keypad */
pxa27x_register_keypad(mpu->kp, map, 0x100);

7
hw/char/omap_uart.c
View File

@ -67,10 +67,9 @@ struct omap_uart_s *omap_uart_init(hwaddr base,
return s;
}
static uint64_t omap_uart_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
struct omap_uart_s *s = opaque;
if (size == 4) {
return omap_badwidth_read8(opaque, addr);
@ -108,7 +107,7 @@ static uint64_t omap_uart_read(void *opaque, hwaddr addr,
static void omap_uart_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
struct omap_uart_s *s = opaque;
if (size == 4) {
omap_badwidth_write8(opaque, addr, value);

15
hw/display/omap_dss.c
View File

@ -175,7 +175,7 @@ void omap_dss_reset(struct omap_dss_s *s)
static uint64_t omap_diss_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
struct omap_dss_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@ -213,7 +213,7 @@ static uint64_t omap_diss_read(void *opaque, hwaddr addr,
static void omap_diss_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
struct omap_dss_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@ -254,7 +254,7 @@ static const MemoryRegionOps omap_diss_ops = {
static uint64_t omap_disc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
struct omap_dss_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@ -379,7 +379,7 @@ static uint64_t omap_disc_read(void *opaque, hwaddr addr,
static void omap_disc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
struct omap_dss_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);
@ -669,10 +669,9 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
struct omap_dss_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@ -739,7 +738,7 @@ static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
static void omap_rfbi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
struct omap_dss_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);

9
hw/display/omap_lcdc.c
View File

@ -198,7 +198,7 @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
static void omap_update_display(void *opaque)
{
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
struct omap_lcd_panel_s *omap_lcd = opaque;
DisplaySurface *surface;
drawfn draw_line;
int size, height, first, last;
@ -376,10 +376,9 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
}
}
static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
struct omap_lcd_panel_s *s = opaque;
switch (addr) {
case 0x00: /* LCD_CONTROL */
@ -412,7 +411,7 @@ static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
static void omap_lcdc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
struct omap_lcd_panel_s *s = opaque;
switch (addr) {
case 0x00: /* LCD_CONTROL */

15
hw/dma/omap_dma.c
View File

@ -1454,10 +1454,9 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
return 0;
}
static uint64_t omap_dma_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
struct omap_dma_s *s = opaque;
int reg, ch;
uint16_t ret;
@ -1505,7 +1504,7 @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr,
static void omap_dma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
struct omap_dma_s *s = opaque;
int reg, ch;
if (size != 2) {
@ -1557,7 +1556,7 @@ static const MemoryRegionOps omap_dma_ops = {
static void omap_dma_request(void *opaque, int drq, int req)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
struct omap_dma_s *s = opaque;
/* The request pins are level triggered in QEMU. */
if (req) {
if (~s->dma->drqbmp & (1ULL << drq)) {
@ -1571,7 +1570,7 @@ static void omap_dma_request(void *opaque, int drq, int req)
/* XXX: this won't be needed once soc_dma knows about clocks. */
static void omap_dma_clk_update(void *opaque, int line, int on)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
struct omap_dma_s *s = opaque;
int i;
s->dma->freq = omap_clk_getrate(s->clk);
@ -1703,7 +1702,7 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
struct omap_dma_s *s = opaque;
int irqn = 0, chnum;
struct omap_dma_channel_s *ch;
@ -1859,7 +1858,7 @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
static void omap_dma4_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
struct omap_dma_s *s = opaque;
int chnum, irqn = 0;
struct omap_dma_channel_s *ch;

48
hw/gpio/omap_gpio.c
View File

@ -41,7 +41,7 @@ struct omap_gpio_s {
uint16_t pins;
};
struct omap_gpif_s {
struct Omap1GpioState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -53,7 +53,8 @@ struct omap_gpif_s {
/* General-Purpose I/O of OMAP1 */
static void omap_gpio_set(void *opaque, int line, int level)
{
struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
Omap1GpioState *p = opaque;
struct omap_gpio_s *s = &p->omap1;
uint16_t prev = s->inputs;
if (level)
@ -71,7 +72,7 @@ static void omap_gpio_set(void *opaque, int line, int level)
static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
struct omap_gpio_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
@ -109,7 +110,7 @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
static void omap_gpio_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
struct omap_gpio_s *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t diff;
int ln;
@ -209,7 +210,7 @@ struct omap2_gpio_s {
uint8_t delay;
};
struct omap2_gpif_s {
struct Omap2GpioState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -273,7 +274,7 @@ static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
static void omap2_gpio_set(void *opaque, int line, int level)
{
struct omap2_gpif_s *p = opaque;
Omap2GpioState *p = opaque;
struct omap2_gpio_s *s = &p->modules[line >> 5];
line &= 31;
@ -308,7 +309,7 @@ static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
struct omap2_gpio_s *s = opaque;
switch (addr) {
case 0x00: /* GPIO_REVISION */
@ -381,7 +382,7 @@ static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
static void omap2_gpio_module_write(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
struct omap2_gpio_s *s = opaque;
uint32_t diff;
int ln;
@ -593,14 +594,14 @@ static const MemoryRegionOps omap2_gpio_module_ops = {
static void omap_gpif_reset(DeviceState *dev)
{
struct omap_gpif_s *s = OMAP1_GPIO(dev);
Omap1GpioState *s = OMAP1_GPIO(dev);
omap_gpio_reset(&s->omap1);
}
static void omap2_gpif_reset(DeviceState *dev)
{
struct omap2_gpif_s *s = OMAP2_GPIO(dev);
Omap2GpioState *s = OMAP2_GPIO(dev);
int i;
for (i = 0; i < s->modulecount; i++) {
@ -610,10 +611,9 @@ static void omap2_gpif_reset(DeviceState *dev)
s->gpo = 0;
}
static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
Omap2GpioState *s = opaque;
switch (addr) {
case 0x00: /* IPGENERICOCPSPL_REVISION */
@ -642,7 +642,7 @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
static void omap2_gpif_top_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
Omap2GpioState *s = opaque;
switch (addr) {
case 0x00: /* IPGENERICOCPSPL_REVISION */
@ -677,7 +677,7 @@ static const MemoryRegionOps omap2_gpif_top_ops = {
static void omap_gpio_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
struct omap_gpif_s *s = OMAP1_GPIO(obj);
Omap1GpioState *s = OMAP1_GPIO(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
qdev_init_gpio_in(dev, omap_gpio_set, 16);
@ -690,7 +690,7 @@ static void omap_gpio_init(Object *obj)
static void omap_gpio_realize(DeviceState *dev, Error **errp)
{
struct omap_gpif_s *s = OMAP1_GPIO(dev);
Omap1GpioState *s = OMAP1_GPIO(dev);
if (!s->clk) {
error_setg(errp, "omap-gpio: clk not connected");
@ -699,7 +699,7 @@ static void omap_gpio_realize(DeviceState *dev, Error **errp)
static void omap2_gpio_realize(DeviceState *dev, Error **errp)
{
struct omap2_gpif_s *s = OMAP2_GPIO(dev);
Omap2GpioState *s = OMAP2_GPIO(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
@ -742,13 +742,13 @@ static void omap2_gpio_realize(DeviceState *dev, Error **errp)
}
}
void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk)
void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk)
{
gpio->clk = clk;
}
static Property omap_gpio_properties[] = {
DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0),
DEFINE_PROP_END_OF_LIST(),
};
@ -766,24 +766,24 @@ static void omap_gpio_class_init(ObjectClass *klass, void *data)
static const TypeInfo omap_gpio_info = {
.name = TYPE_OMAP1_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct omap_gpif_s),
.instance_size = sizeof(Omap1GpioState),
.instance_init = omap_gpio_init,
.class_init = omap_gpio_class_init,
};
void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk)
void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk)
{
gpio->iclk = clk;
}
void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk)
void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk)
{
assert(i <= 5);
gpio->fclk[i] = clk;
}
static Property omap2_gpio_properties[] = {
DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
DEFINE_PROP_INT32("mpu_model", Omap2GpioState, mpu_model, 0),
DEFINE_PROP_END_OF_LIST(),
};
@ -801,7 +801,7 @@ static void omap2_gpio_class_init(ObjectClass *klass, void *data)
static const TypeInfo omap2_gpio_info = {
.name = TYPE_OMAP2_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct omap2_gpif_s),
.instance_size = sizeof(Omap2GpioState),
.class_init = omap2_gpio_class_init,
};

4
hw/i2c/Kconfig
View File

@ -34,6 +34,10 @@ config MPC_I2C
bool
select I2C
config ALLWINNER_I2C
bool
select I2C
config PCA954X
bool
select I2C

459
hw/i2c/allwinner-i2c.c Normal file
View File

@ -0,0 +1,459 @@
/*
* Allwinner I2C Bus Serial Interface Emulation
*
* Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
*
* This file is derived from IMX I2C controller,
* by Jean-Christophe DUBOIS .
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
* SPDX-License-Identifier: MIT
*/
#include "qemu/osdep.h"
#include "hw/i2c/allwinner-i2c.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "hw/i2c/i2c.h"
#include "qemu/log.h"
#include "trace.h"
#include "qemu/module.h"
/* Allwinner I2C memory map */
#define TWI_ADDR_REG 0x00 /* slave address register */
#define TWI_XADDR_REG 0x04 /* extended slave address register */
#define TWI_DATA_REG 0x08 /* data register */
#define TWI_CNTR_REG 0x0c /* control register */
#define TWI_STAT_REG 0x10 /* status register */
#define TWI_CCR_REG 0x14 /* clock control register */
#define TWI_SRST_REG 0x18 /* software reset register */
#define TWI_EFR_REG 0x1c /* enhance feature register */
#define TWI_LCR_REG 0x20 /* line control register */
/* Used only in slave mode, do not set */
#define TWI_ADDR_RESET 0
#define TWI_XADDR_RESET 0
/* Data register */
#define TWI_DATA_MASK 0xFF
#define TWI_DATA_RESET 0
/* Control register */
#define TWI_CNTR_INT_EN (1 << 7)
#define TWI_CNTR_BUS_EN (1 << 6)
#define TWI_CNTR_M_STA (1 << 5)
#define TWI_CNTR_M_STP (1 << 4)
#define TWI_CNTR_INT_FLAG (1 << 3)
#define TWI_CNTR_A_ACK (1 << 2)
#define TWI_CNTR_MASK 0xFC
#define TWI_CNTR_RESET 0
/* Status register */
#define TWI_STAT_MASK 0xF8
#define TWI_STAT_RESET 0xF8
/* Clock register */
#define TWI_CCR_CLK_M_MASK 0x78
#define TWI_CCR_CLK_N_MASK 0x07
#define TWI_CCR_MASK 0x7F
#define TWI_CCR_RESET 0
/* Soft reset */
#define TWI_SRST_MASK 0x01
#define TWI_SRST_RESET 0
/* Enhance feature */
#define TWI_EFR_MASK 0x03
#define TWI_EFR_RESET 0
/* Line control */
#define TWI_LCR_SCL_STATE (1 << 5)
#define TWI_LCR_SDA_STATE (1 << 4)
#define TWI_LCR_SCL_CTL (1 << 3)
#define TWI_LCR_SCL_CTL_EN (1 << 2)
#define TWI_LCR_SDA_CTL (1 << 1)
#define TWI_LCR_SDA_CTL_EN (1 << 0)
#define TWI_LCR_MASK 0x3F
#define TWI_LCR_RESET 0x3A
/* Status value in STAT register is shifted by 3 bits */
#define TWI_STAT_SHIFT 3
#define STAT_FROM_STA(x) ((x) << TWI_STAT_SHIFT)
#define STAT_TO_STA(x) ((x) >> TWI_STAT_SHIFT)
enum {
STAT_BUS_ERROR = 0,
/* Master mode */
STAT_M_STA_TX,
STAT_M_RSTA_TX,
STAT_M_ADDR_WR_ACK,
STAT_M_ADDR_WR_NACK,
STAT_M_DATA_TX_ACK,
STAT_M_DATA_TX_NACK,
STAT_M_ARB_LOST,
STAT_M_ADDR_RD_ACK,
STAT_M_ADDR_RD_NACK,
STAT_M_DATA_RX_ACK,
STAT_M_DATA_RX_NACK,
/* Slave mode */
STAT_S_ADDR_WR_ACK,
STAT_S_ARB_LOST_AW_ACK,
STAT_S_GCA_ACK,
STAT_S_ARB_LOST_GCA_ACK,
STAT_S_DATA_RX_SA_ACK,
STAT_S_DATA_RX_SA_NACK,
STAT_S_DATA_RX_GCA_ACK,
STAT_S_DATA_RX_GCA_NACK,
STAT_S_STP_RSTA,
STAT_S_ADDR_RD_ACK,
STAT_S_ARB_LOST_AR_ACK,
STAT_S_DATA_TX_ACK,
STAT_S_DATA_TX_NACK,
STAT_S_LB_TX_ACK,
/* Master mode, 10-bit */
STAT_M_2ND_ADDR_WR_ACK,
STAT_M_2ND_ADDR_WR_NACK,
/* Idle */
STAT_IDLE = 0x1f
} TWI_STAT_STA;
static const char *allwinner_i2c_get_regname(unsigned offset)
{
switch (offset) {
case TWI_ADDR_REG:
return "ADDR";
case TWI_XADDR_REG:
return "XADDR";
case TWI_DATA_REG:
return "DATA";
case TWI_CNTR_REG:
return "CNTR";
case TWI_STAT_REG:
return "STAT";
case TWI_CCR_REG:
return "CCR";
case TWI_SRST_REG:
return "SRST";
case TWI_EFR_REG:
return "EFR";
case TWI_LCR_REG:
return "LCR";
default:
return "[?]";
}
}
static inline bool allwinner_i2c_is_reset(AWI2CState *s)
{
return s->srst & TWI_SRST_MASK;
}
static inline bool allwinner_i2c_bus_is_enabled(AWI2CState *s)
{
return s->cntr & TWI_CNTR_BUS_EN;
}
static inline bool allwinner_i2c_interrupt_is_enabled(AWI2CState *s)
{
return s->cntr & TWI_CNTR_INT_EN;
}
static void allwinner_i2c_reset_hold(Object *obj)
{
AWI2CState *s = AW_I2C(obj);
if (STAT_TO_STA(s->stat) != STAT_IDLE) {
i2c_end_transfer(s->bus);
}
s->addr = TWI_ADDR_RESET;
s->xaddr = TWI_XADDR_RESET;
s->data = TWI_DATA_RESET;
s->cntr = TWI_CNTR_RESET;
s->stat = TWI_STAT_RESET;
s->ccr = TWI_CCR_RESET;
s->srst = TWI_SRST_RESET;
s->efr = TWI_EFR_RESET;
s->lcr = TWI_LCR_RESET;
}
static inline void allwinner_i2c_raise_interrupt(AWI2CState *s)
{
/*
* Raise an interrupt if the device is not reset and it is configured
* to generate some interrupts.
*/
if (!allwinner_i2c_is_reset(s) && allwinner_i2c_bus_is_enabled(s)) {
if (STAT_TO_STA(s->stat) != STAT_IDLE) {
s->cntr |= TWI_CNTR_INT_FLAG;
if (allwinner_i2c_interrupt_is_enabled(s)) {
qemu_irq_raise(s->irq);
}
}
}
}
static uint64_t allwinner_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
uint16_t value;
AWI2CState *s = AW_I2C(opaque);
switch (offset) {
case TWI_ADDR_REG:
value = s->addr;
break;
case TWI_XADDR_REG:
value = s->xaddr;
break;
case TWI_DATA_REG:
if ((STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) ||
(STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) ||
(STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK)) {
/* Get the next byte */
s->data = i2c_recv(s->bus);
if (s->cntr & TWI_CNTR_A_ACK) {
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
} else {
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
}
allwinner_i2c_raise_interrupt(s);
}
value = s->data;
break;
case TWI_CNTR_REG:
value = s->cntr;
break;
case TWI_STAT_REG:
value = s->stat;
/*
* If polling when reading then change state to indicate data
* is available
*/
if (STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) {
if (s->cntr & TWI_CNTR_A_ACK) {
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
} else {
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
}
allwinner_i2c_raise_interrupt(s);
}
break;
case TWI_CCR_REG:
value = s->ccr;
break;
case TWI_SRST_REG:
value = s->srst;
break;
case TWI_EFR_REG:
value = s->efr;
break;
case TWI_LCR_REG:
value = s->lcr;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
value = 0;
break;
}
trace_allwinner_i2c_read(allwinner_i2c_get_regname(offset), offset, value);
return (uint64_t)value;
}
static void allwinner_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
AWI2CState *s = AW_I2C(opaque);
value &= 0xff;
trace_allwinner_i2c_write(allwinner_i2c_get_regname(offset), offset, value);
switch (offset) {
case TWI_ADDR_REG:
s->addr = (uint8_t)value;
break;
case TWI_XADDR_REG:
s->xaddr = (uint8_t)value;
break;
case TWI_DATA_REG:
/* If the device is in reset or not enabled, nothing to do */
if (allwinner_i2c_is_reset(s) || (!allwinner_i2c_bus_is_enabled(s))) {
break;
}
s->data = value & TWI_DATA_MASK;
switch (STAT_TO_STA(s->stat)) {
case STAT_M_STA_TX:
case STAT_M_RSTA_TX:
/* Send address */
if (i2c_start_transfer(s->bus, extract32(s->data, 1, 7),
extract32(s->data, 0, 1))) {
/* If non zero is returned, the address is not valid */
s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_NACK);
} else {
/* Determine if read of write */
if (extract32(s->data, 0, 1)) {
s->stat = STAT_FROM_STA(STAT_M_ADDR_RD_ACK);
} else {
s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_ACK);
}
allwinner_i2c_raise_interrupt(s);
}
break;
case STAT_M_ADDR_WR_ACK:
case STAT_M_DATA_TX_ACK:
if (i2c_send(s->bus, s->data)) {
/* If the target return non zero then end the transfer */
s->stat = STAT_FROM_STA(STAT_M_DATA_TX_NACK);
i2c_end_transfer(s->bus);
} else {
s->stat = STAT_FROM_STA(STAT_M_DATA_TX_ACK);
allwinner_i2c_raise_interrupt(s);
}
break;
default:
break;
}
break;
case TWI_CNTR_REG:
if (!allwinner_i2c_is_reset(s)) {
/* Do something only if not in software reset */
s->cntr = value & TWI_CNTR_MASK;
/* Check if start condition should be sent */
if (s->cntr & TWI_CNTR_M_STA) {
/* Update status */
if (STAT_TO_STA(s->stat) == STAT_IDLE) {
/* Send start condition */
s->stat = STAT_FROM_STA(STAT_M_STA_TX);
} else {
/* Send repeated start condition */
s->stat = STAT_FROM_STA(STAT_M_RSTA_TX);
}
/* Clear start condition */
s->cntr &= ~TWI_CNTR_M_STA;
}
if (s->cntr & TWI_CNTR_M_STP) {
/* Update status */
i2c_end_transfer(s->bus);
s->stat = STAT_FROM_STA(STAT_IDLE);
s->cntr &= ~TWI_CNTR_M_STP;
}
if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
/* Interrupt flag cleared */
qemu_irq_lower(s->irq);
}
if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
}
} else {
if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK) {
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
}
}
allwinner_i2c_raise_interrupt(s);
}
break;
case TWI_CCR_REG:
s->ccr = value & TWI_CCR_MASK;
break;
case TWI_SRST_REG:
if (((value & TWI_SRST_MASK) == 0) && (s->srst & TWI_SRST_MASK)) {
/* Perform reset */
allwinner_i2c_reset_hold(OBJECT(s));
}
s->srst = value & TWI_SRST_MASK;
break;
case TWI_EFR_REG:
s->efr = value & TWI_EFR_MASK;
break;
case TWI_LCR_REG:
s->lcr = value & TWI_LCR_MASK;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
break;
}
}
static const MemoryRegionOps allwinner_i2c_ops = {
.read = allwinner_i2c_read,
.write = allwinner_i2c_write,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription allwinner_i2c_vmstate = {
.name = TYPE_AW_I2C,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(addr, AWI2CState),
VMSTATE_UINT8(xaddr, AWI2CState),
VMSTATE_UINT8(data, AWI2CState),
VMSTATE_UINT8(cntr, AWI2CState),
VMSTATE_UINT8(ccr, AWI2CState),
VMSTATE_UINT8(srst, AWI2CState),
VMSTATE_UINT8(efr, AWI2CState),
VMSTATE_UINT8(lcr, AWI2CState),
VMSTATE_END_OF_LIST()
}
};
static void allwinner_i2c_realize(DeviceState *dev, Error **errp)
{
AWI2CState *s = AW_I2C(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_i2c_ops, s,
TYPE_AW_I2C, AW_I2C_MEM_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
s->bus = i2c_init_bus(dev, "i2c");
}
static void allwinner_i2c_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
rc->phases.hold = allwinner_i2c_reset_hold;
dc->vmsd = &allwinner_i2c_vmstate;
dc->realize = allwinner_i2c_realize;
dc->desc = "Allwinner I2C Controller";
}
static const TypeInfo allwinner_i2c_type_info = {
.name = TYPE_AW_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AWI2CState),
.class_init = allwinner_i2c_class_init,
};
static void allwinner_i2c_register_types(void)
{
type_register_static(&allwinner_i2c_type_info);
}
type_init(allwinner_i2c_register_types)

1
hw/i2c/meson.build
View File

@ -8,6 +8,7 @@ i2c_ss.add(when: 'CONFIG_BITBANG_I2C', if_true: files('bitbang_i2c.c'))
i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c'))
i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c'))
i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c'))
i2c_ss.add(when: 'CONFIG_ALLWINNER_I2C', if_true: files('allwinner-i2c.c'))
i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c'))
i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c'))
i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c'))

5
hw/i2c/trace-events
View File

@ -8,6 +8,11 @@ i2c_send_async(uint8_t address, uint8_t data) "send_async(addr:0x%02x) data:0x%0
i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x"
i2c_ack(void) ""
# allwinner_i2c.c
allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value) "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64
allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value) "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64
# aspeed_i2c.c
aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status) "handling cmd=0x%x %s count=%d intr=0x%x"

38
hw/intc/omap_intc.c
View File

@ -38,7 +38,7 @@ struct omap_intr_handler_bank_s {
unsigned char priority[32];
};
struct omap_intr_handler_s {
struct OMAPIntcState {
SysBusDevice parent_obj;
qemu_irq *pins;
@ -60,7 +60,7 @@ struct omap_intr_handler_s {
struct omap_intr_handler_bank_s bank[3];
};
static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq)
{
int i, j, sir_intr, p_intr, p;
uint32_t level;
@ -88,7 +88,7 @@ static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
s->sir_intr[is_fiq] = sir_intr;
}
static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
static inline void omap_inth_update(OMAPIntcState *s, int is_fiq)
{
int i;
uint32_t has_intr = 0;
@ -109,7 +109,7 @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
static void omap_set_intr(void *opaque, int irq, int req)
{
struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
OMAPIntcState *ih = opaque;
uint32_t rise;
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
@ -136,7 +136,7 @@ static void omap_set_intr(void *opaque, int irq, int req)
/* Simplified version with no edge detection */
static void omap_set_intr_noedge(void *opaque, int irq, int req)
{
struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
OMAPIntcState *ih = opaque;
uint32_t rise;
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
@ -156,7 +156,7 @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
static uint64_t omap_inth_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
OMAPIntcState *s = opaque;
int i, offset = addr;
int bank_no = offset >> 8;
int line_no;
@ -234,7 +234,7 @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
static void omap_inth_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
OMAPIntcState *s = opaque;
int i, offset = addr;
int bank_no = offset >> 8;
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
@ -336,7 +336,7 @@ static const MemoryRegionOps omap_inth_mem_ops = {
static void omap_inth_reset(DeviceState *dev)
{
struct omap_intr_handler_s *s = OMAP_INTC(dev);
OMAPIntcState *s = OMAP_INTC(dev);
int i;
for (i = 0; i < s->nbanks; ++i){
@ -366,7 +366,7 @@ static void omap_inth_reset(DeviceState *dev)
static void omap_intc_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
struct omap_intr_handler_s *s = OMAP_INTC(obj);
OMAPIntcState *s = OMAP_INTC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
s->nbanks = 1;
@ -380,25 +380,25 @@ static void omap_intc_init(Object *obj)
static void omap_intc_realize(DeviceState *dev, Error **errp)
{
struct omap_intr_handler_s *s = OMAP_INTC(dev);
OMAPIntcState *s = OMAP_INTC(dev);
if (!s->iclk) {
error_setg(errp, "omap-intc: clk not connected");
}
}
void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk)
void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk)
{
intc->iclk = clk;
}
void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk)
void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk)
{
intc->fclk = clk;
}
static Property omap_intc_properties[] = {
DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
DEFINE_PROP_UINT32("size", OMAPIntcState, size, 0x100),
DEFINE_PROP_END_OF_LIST(),
};
@ -423,7 +423,7 @@ static const TypeInfo omap_intc_info = {
static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
OMAPIntcState *s = opaque;
int offset = addr;
int bank_no, line_no;
struct omap_intr_handler_bank_s *bank = NULL;
@ -504,7 +504,7 @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
static void omap2_inth_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
OMAPIntcState *s = opaque;
int offset = addr;
int bank_no, line_no;
struct omap_intr_handler_bank_s *bank = NULL;
@ -622,7 +622,7 @@ static const MemoryRegionOps omap2_inth_mem_ops = {
static void omap2_intc_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
struct omap_intr_handler_s *s = OMAP_INTC(obj);
OMAPIntcState *s = OMAP_INTC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
s->level_only = 1;
@ -637,7 +637,7 @@ static void omap2_intc_init(Object *obj)
static void omap2_intc_realize(DeviceState *dev, Error **errp)
{
struct omap_intr_handler_s *s = OMAP_INTC(dev);
OMAPIntcState *s = OMAP_INTC(dev);
if (!s->iclk) {
error_setg(errp, "omap2-intc: iclk not connected");
@ -650,7 +650,7 @@ static void omap2_intc_realize(DeviceState *dev, Error **errp)
}
static Property omap2_intc_properties[] = {
DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
DEFINE_PROP_UINT8("revision", OMAPIntcState,
revision, 0x21),
DEFINE_PROP_END_OF_LIST(),
};
@ -676,7 +676,7 @@ static const TypeInfo omap2_intc_info = {
static const TypeInfo omap_intc_type_info = {
.name = TYPE_OMAP_INTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(omap_intr_handler),
.instance_size = sizeof(OMAPIntcState),
.abstract = true,
};

28
hw/intc/xilinx_intc.c
View File

@ -42,10 +42,10 @@
#define R_MAX 8
#define TYPE_XILINX_INTC "xlnx.xps-intc"
DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
TYPE_XILINX_INTC)
typedef struct XpsIntc XpsIntc;
DECLARE_INSTANCE_CHECKER(XpsIntc, XILINX_INTC, TYPE_XILINX_INTC)
struct xlx_pic
struct XpsIntc
{
SysBusDevice parent_obj;
@ -62,7 +62,7 @@ struct xlx_pic
uint32_t irq_pin_state;
};
static void update_irq(struct xlx_pic *p)
static void update_irq(XpsIntc *p)
{
uint32_t i;
@ -87,10 +87,9 @@ static void update_irq(struct xlx_pic *p)
qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
}
static uint64_t
pic_read(void *opaque, hwaddr addr, unsigned int size)
static uint64_t pic_read(void *opaque, hwaddr addr, unsigned int size)
{
struct xlx_pic *p = opaque;
XpsIntc *p = opaque;
uint32_t r = 0;
addr >>= 2;
@ -106,11 +105,10 @@ pic_read(void *opaque, hwaddr addr, unsigned int size)
return r;
}
static void
pic_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
static void pic_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_pic *p = opaque;
XpsIntc *p = opaque;
uint32_t value = val64;
addr >>= 2;
@ -154,7 +152,7 @@ static const MemoryRegionOps pic_ops = {
static void irq_handler(void *opaque, int irq, int level)
{
struct xlx_pic *p = opaque;
XpsIntc *p = opaque;
/* edge triggered interrupt */
if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
@ -168,7 +166,7 @@ static void irq_handler(void *opaque, int irq, int level)
static void xilinx_intc_init(Object *obj)
{
struct xlx_pic *p = XILINX_INTC(obj);
XpsIntc *p = XILINX_INTC(obj);
qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
@ -179,7 +177,7 @@ static void xilinx_intc_init(Object *obj)
}
static Property xilinx_intc_properties[] = {
DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
DEFINE_PROP_END_OF_LIST(),
};
@ -193,7 +191,7 @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
static const TypeInfo xilinx_intc_info = {
.name = TYPE_XILINX_INTC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct xlx_pic),
.instance_size = sizeof(XpsIntc),
.instance_init = xilinx_intc_init,
.class_init = xilinx_intc_class_init,
};

10
hw/misc/Kconfig
View File

@ -174,4 +174,14 @@ config VIRT_CTRL
config LASI
bool
config ALLWINNER_A10_CCM
bool
config ALLWINNER_A10_DRAMC
bool
config AXP209_PMU
bool
depends on I2C
source macio/Kconfig

224
hw/misc/allwinner-a10-ccm.c Normal file
View File

@ -0,0 +1,224 @@
/*
* Allwinner A10 Clock Control Module emulation
*
* Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
*
* This file is derived from Allwinner H3 CCU,
* by Niek Linnenbank.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/misc/allwinner-a10-ccm.h"
/* CCM register offsets */
enum {
REG_PLL1_CFG = 0x0000, /* PLL1 Control */
REG_PLL1_TUN = 0x0004, /* PLL1 Tuning */
REG_PLL2_CFG = 0x0008, /* PLL2 Control */
REG_PLL2_TUN = 0x000C, /* PLL2 Tuning */
REG_PLL3_CFG = 0x0010, /* PLL3 Control */
REG_PLL4_CFG = 0x0018, /* PLL4 Control */
REG_PLL5_CFG = 0x0020, /* PLL5 Control */
REG_PLL5_TUN = 0x0024, /* PLL5 Tuning */
REG_PLL6_CFG = 0x0028, /* PLL6 Control */
REG_PLL6_TUN = 0x002C, /* PLL6 Tuning */
REG_PLL7_CFG = 0x0030, /* PLL7 Control */
REG_PLL1_TUN2 = 0x0038, /* PLL1 Tuning2 */
REG_PLL5_TUN2 = 0x003C, /* PLL5 Tuning2 */
REG_PLL8_CFG = 0x0040, /* PLL8 Control */
REG_OSC24M_CFG = 0x0050, /* OSC24M Control */
REG_CPU_AHB_APB0_CFG = 0x0054, /* CPU, AHB and APB0 Divide Ratio */
};
#define REG_INDEX(offset) (offset / sizeof(uint32_t))
/* CCM register reset values */
enum {
REG_PLL1_CFG_RST = 0x21005000,
REG_PLL1_TUN_RST = 0x0A101000,
REG_PLL2_CFG_RST = 0x08100010,
REG_PLL2_TUN_RST = 0x00000000,
REG_PLL3_CFG_RST = 0x0010D063,
REG_PLL4_CFG_RST = 0x21009911,
REG_PLL5_CFG_RST = 0x11049280,
REG_PLL5_TUN_RST = 0x14888000,
REG_PLL6_CFG_RST = 0x21009911,
REG_PLL6_TUN_RST = 0x00000000,
REG_PLL7_CFG_RST = 0x0010D063,
REG_PLL1_TUN2_RST = 0x00000000,
REG_PLL5_TUN2_RST = 0x00000000,
REG_PLL8_CFG_RST = 0x21009911,
REG_OSC24M_CFG_RST = 0x00138013,
REG_CPU_AHB_APB0_CFG_RST = 0x00010010,
};
static uint64_t allwinner_a10_ccm_read(void *opaque, hwaddr offset,
unsigned size)
{
const AwA10ClockCtlState *s = AW_A10_CCM(opaque);
const uint32_t idx = REG_INDEX(offset);
switch (offset) {
case REG_PLL1_CFG:
case REG_PLL1_TUN:
case REG_PLL2_CFG:
case REG_PLL2_TUN:
case REG_PLL3_CFG:
case REG_PLL4_CFG:
case REG_PLL5_CFG:
case REG_PLL5_TUN:
case REG_PLL6_CFG:
case REG_PLL6_TUN:
case REG_PLL7_CFG:
case REG_PLL1_TUN2:
case REG_PLL5_TUN2:
case REG_PLL8_CFG:
case REG_OSC24M_CFG:
case REG_CPU_AHB_APB0_CFG:
break;
case 0x158 ... AW_A10_CCM_IOSIZE:
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
__func__, (uint32_t)offset);
return 0;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
__func__, (uint32_t)offset);
return 0;
}
return s->regs[idx];
}
static void allwinner_a10_ccm_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
AwA10ClockCtlState *s = AW_A10_CCM(opaque);
const uint32_t idx = REG_INDEX(offset);
switch (offset) {
case REG_PLL1_CFG:
case REG_PLL1_TUN:
case REG_PLL2_CFG:
case REG_PLL2_TUN:
case REG_PLL3_CFG:
case REG_PLL4_CFG:
case REG_PLL5_CFG:
case REG_PLL5_TUN:
case REG_PLL6_CFG:
case REG_PLL6_TUN:
case REG_PLL7_CFG:
case REG_PLL1_TUN2:
case REG_PLL5_TUN2:
case REG_PLL8_CFG:
case REG_OSC24M_CFG:
case REG_CPU_AHB_APB0_CFG:
break;
case 0x158 ... AW_A10_CCM_IOSIZE:
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
__func__, (uint32_t)offset);
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
__func__, (uint32_t)offset);
break;
}
s->regs[idx] = (uint32_t) val;
}
static const MemoryRegionOps allwinner_a10_ccm_ops = {
.read = allwinner_a10_ccm_read,
.write = allwinner_a10_ccm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
.impl.min_access_size = 4,
};
static void allwinner_a10_ccm_reset_enter(Object *obj, ResetType type)
{
AwA10ClockCtlState *s = AW_A10_CCM(obj);
/* Set default values for registers */
s->regs[REG_INDEX(REG_PLL1_CFG)] = REG_PLL1_CFG_RST;
s->regs[REG_INDEX(REG_PLL1_TUN)] = REG_PLL1_TUN_RST;
s->regs[REG_INDEX(REG_PLL2_CFG)] = REG_PLL2_CFG_RST;
s->regs[REG_INDEX(REG_PLL2_TUN)] = REG_PLL2_TUN_RST;
s->regs[REG_INDEX(REG_PLL3_CFG)] = REG_PLL3_CFG_RST;
s->regs[REG_INDEX(REG_PLL4_CFG)] = REG_PLL4_CFG_RST;
s->regs[REG_INDEX(REG_PLL5_CFG)] = REG_PLL5_CFG_RST;
s->regs[REG_INDEX(REG_PLL5_TUN)] = REG_PLL5_TUN_RST;
s->regs[REG_INDEX(REG_PLL6_CFG)] = REG_PLL6_CFG_RST;
s->regs[REG_INDEX(REG_PLL6_TUN)] = REG_PLL6_TUN_RST;
s->regs[REG_INDEX(REG_PLL7_CFG)] = REG_PLL7_CFG_RST;
s->regs[REG_INDEX(REG_PLL1_TUN2)] = REG_PLL1_TUN2_RST;
s->regs[REG_INDEX(REG_PLL5_TUN2)] = REG_PLL5_TUN2_RST;
s->regs[REG_INDEX(REG_PLL8_CFG)] = REG_PLL8_CFG_RST;
s->regs[REG_INDEX(REG_OSC24M_CFG)] = REG_OSC24M_CFG_RST;
s->regs[REG_INDEX(REG_CPU_AHB_APB0_CFG)] = REG_CPU_AHB_APB0_CFG_RST;
}
static void allwinner_a10_ccm_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
AwA10ClockCtlState *s = AW_A10_CCM(obj);
/* Memory mapping */
memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_ccm_ops, s,
TYPE_AW_A10_CCM, AW_A10_CCM_IOSIZE);
sysbus_init_mmio(sbd, &s->iomem);
}
static const VMStateDescription allwinner_a10_ccm_vmstate = {
.name = "allwinner-a10-ccm",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AwA10ClockCtlState, AW_A10_CCM_REGS_NUM),
VMSTATE_END_OF_LIST()
}
};
static void allwinner_a10_ccm_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
rc->phases.enter = allwinner_a10_ccm_reset_enter;
dc->vmsd = &allwinner_a10_ccm_vmstate;
}
static const TypeInfo allwinner_a10_ccm_info = {
.name = TYPE_AW_A10_CCM,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_init = allwinner_a10_ccm_init,
.instance_size = sizeof(AwA10ClockCtlState),
.class_init = allwinner_a10_ccm_class_init,
};
static void allwinner_a10_ccm_register(void)
{
type_register_static(&allwinner_a10_ccm_info);
}
type_init(allwinner_a10_ccm_register)

179
hw/misc/allwinner-a10-dramc.c Normal file
View File

@ -0,0 +1,179 @@
/*
* Allwinner A10 DRAM Controller emulation
*
* Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
*
* This file is derived from Allwinner H3 DRAMC,
* by Niek Linnenbank.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/misc/allwinner-a10-dramc.h"
/* DRAMC register offsets */
enum {
REG_SDR_CCR = 0x0000,
REG_SDR_ZQCR0 = 0x00a8,
REG_SDR_ZQSR = 0x00b0
};
#define REG_INDEX(offset) (offset / sizeof(uint32_t))
/* DRAMC register flags */
enum {
REG_SDR_CCR_DATA_TRAINING = (1 << 30),
REG_SDR_CCR_DRAM_INIT = (1 << 31),
};
enum {
REG_SDR_ZQSR_ZCAL = (1 << 31),
};
/* DRAMC register reset values */
enum {
REG_SDR_CCR_RESET = 0x80020000,
REG_SDR_ZQCR0_RESET = 0x07b00000,
REG_SDR_ZQSR_RESET = 0x80000000
};
static uint64_t allwinner_a10_dramc_read(void *opaque, hwaddr offset,
unsigned size)
{
const AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
const uint32_t idx = REG_INDEX(offset);
switch (offset) {
case REG_SDR_CCR:
case REG_SDR_ZQCR0:
case REG_SDR_ZQSR:
break;
case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
__func__, (uint32_t)offset);
return 0;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
__func__, (uint32_t)offset);
return 0;
}
return s->regs[idx];
}
static void allwinner_a10_dramc_write(void *opaque, hwaddr offset,
uint64_t val, unsigned size)
{
AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
const uint32_t idx = REG_INDEX(offset);
switch (offset) {
case REG_SDR_CCR:
if (val & REG_SDR_CCR_DRAM_INIT) {
/* Clear DRAM_INIT to indicate process is done. */
val &= ~REG_SDR_CCR_DRAM_INIT;
}
if (val & REG_SDR_CCR_DATA_TRAINING) {
/* Clear DATA_TRAINING to indicate process is done. */
val &= ~REG_SDR_CCR_DATA_TRAINING;
}
break;
case REG_SDR_ZQCR0:
/* Set ZCAL in ZQSR to indicate calibration is done. */
s->regs[REG_INDEX(REG_SDR_ZQSR)] |= REG_SDR_ZQSR_ZCAL;
break;
case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
__func__, (uint32_t)offset);
break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
__func__, (uint32_t)offset);
break;
}
s->regs[idx] = (uint32_t) val;
}
static const MemoryRegionOps allwinner_a10_dramc_ops = {
.read = allwinner_a10_dramc_read,
.write = allwinner_a10_dramc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
.impl.min_access_size = 4,
};
static void allwinner_a10_dramc_reset_enter(Object *obj, ResetType type)
{
AwA10DramControllerState *s = AW_A10_DRAMC(obj);
/* Set default values for registers */
s->regs[REG_INDEX(REG_SDR_CCR)] = REG_SDR_CCR_RESET;
s->regs[REG_INDEX(REG_SDR_ZQCR0)] = REG_SDR_ZQCR0_RESET;
s->regs[REG_INDEX(REG_SDR_ZQSR)] = REG_SDR_ZQSR_RESET;
}
static void allwinner_a10_dramc_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
AwA10DramControllerState *s = AW_A10_DRAMC(obj);
/* Memory mapping */
memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_dramc_ops, s,
TYPE_AW_A10_DRAMC, AW_A10_DRAMC_IOSIZE);
sysbus_init_mmio(sbd, &s->iomem);
}
static const VMStateDescription allwinner_a10_dramc_vmstate = {
.name = "allwinner-a10-dramc",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AwA10DramControllerState,
AW_A10_DRAMC_REGS_NUM),
VMSTATE_END_OF_LIST()
}
};
static void allwinner_a10_dramc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
rc->phases.enter = allwinner_a10_dramc_reset_enter;
dc->vmsd = &allwinner_a10_dramc_vmstate;
}
static const TypeInfo allwinner_a10_dramc_info = {
.name = TYPE_AW_A10_DRAMC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_init = allwinner_a10_dramc_init,
.instance_size = sizeof(AwA10DramControllerState),
.class_init = allwinner_a10_dramc_class_init,
};
static void allwinner_a10_dramc_register(void)
{
type_register_static(&allwinner_a10_dramc_info);
}
type_init(allwinner_a10_dramc_register)

238
hw/misc/axp209.c Normal file
View File

@ -0,0 +1,238 @@
/*
* AXP-209 PMU Emulation
*
* Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* SPDX-License-Identifier: MIT
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "trace.h"
#include "hw/i2c/i2c.h"
#include "migration/vmstate.h"
#define TYPE_AXP209_PMU "axp209_pmu"
#define AXP209(obj) \
OBJECT_CHECK(AXP209I2CState, (obj), TYPE_AXP209_PMU)
/* registers */
enum {
REG_POWER_STATUS = 0x0u,
REG_OPERATING_MODE,
REG_OTG_VBUS_STATUS,
REG_CHIP_VERSION,
REG_DATA_CACHE_0,
REG_DATA_CACHE_1,
REG_DATA_CACHE_2,
REG_DATA_CACHE_3,
REG_DATA_CACHE_4,
REG_DATA_CACHE_5,
REG_DATA_CACHE_6,
REG_DATA_CACHE_7,
REG_DATA_CACHE_8,
REG_DATA_CACHE_9,
REG_DATA_CACHE_A,
REG_DATA_CACHE_B,
REG_POWER_OUTPUT_CTRL = 0x12u,
REG_DC_DC2_OUT_V_CTRL = 0x23u,
REG_DC_DC2_DVS_CTRL = 0x25u,
REG_DC_DC3_OUT_V_CTRL = 0x27u,
REG_LDO2_4_OUT_V_CTRL,
REG_LDO3_OUT_V_CTRL,
REG_VBUS_CH_MGMT = 0x30u,
REG_SHUTDOWN_V_CTRL,
REG_SHUTDOWN_CTRL,
REG_CHARGE_CTRL_1,
REG_CHARGE_CTRL_2,
REG_SPARE_CHARGE_CTRL,
REG_PEK_KEY_CTRL,
REG_DC_DC_FREQ_SET,
REG_CHR_TEMP_TH_SET,
REG_CHR_HIGH_TEMP_TH_CTRL,
REG_IPSOUT_WARN_L1,
REG_IPSOUT_WARN_L2,
REG_DISCHR_TEMP_TH_SET,
REG_DISCHR_HIGH_TEMP_TH_CTRL,
REG_IRQ_BANK_1_CTRL = 0x40u,
REG_IRQ_BANK_2_CTRL,
REG_IRQ_BANK_3_CTRL,
REG_IRQ_BANK_4_CTRL,
REG_IRQ_BANK_5_CTRL,
REG_IRQ_BANK_1_STAT = 0x48u,
REG_IRQ_BANK_2_STAT,
REG_IRQ_BANK_3_STAT,
REG_IRQ_BANK_4_STAT,
REG_IRQ_BANK_5_STAT,
REG_ADC_ACIN_V_H = 0x56u,
REG_ADC_ACIN_V_L,
REG_ADC_ACIN_CURR_H,
REG_ADC_ACIN_CURR_L,
REG_ADC_VBUS_V_H,
REG_ADC_VBUS_V_L,
REG_ADC_VBUS_CURR_H,
REG_ADC_VBUS_CURR_L,
REG_ADC_INT_TEMP_H,
REG_ADC_INT_TEMP_L,
REG_ADC_TEMP_SENS_V_H = 0x62u,
REG_ADC_TEMP_SENS_V_L,
REG_ADC_BAT_V_H = 0x78u,
REG_ADC_BAT_V_L,
REG_ADC_BAT_DISCHR_CURR_H,
REG_ADC_BAT_DISCHR_CURR_L,
REG_ADC_BAT_CHR_CURR_H,
REG_ADC_BAT_CHR_CURR_L,
REG_ADC_IPSOUT_V_H,
REG_ADC_IPSOUT_V_L,
REG_DC_DC_MOD_SEL = 0x80u,
REG_ADC_EN_1,
REG_ADC_EN_2,
REG_ADC_SR_CTRL,
REG_ADC_IN_RANGE,
REG_GPIO1_ADC_IRQ_RISING_TH,
REG_GPIO1_ADC_IRQ_FALLING_TH,
REG_TIMER_CTRL = 0x8au,
REG_VBUS_CTRL_MON_SRP,
REG_OVER_TEMP_SHUTDOWN = 0x8fu,
REG_GPIO0_FEAT_SET,
REG_GPIO_OUT_HIGH_SET,
REG_GPIO1_FEAT_SET,
REG_GPIO2_FEAT_SET,
REG_GPIO_SIG_STATE_SET_MON,
REG_GPIO3_SET,
REG_COULOMB_CNTR_CTRL = 0xb8u,
REG_POWER_MEAS_RES,
NR_REGS
};
#define AXP209_CHIP_VERSION_ID (0x01)
#define AXP209_DC_DC2_OUT_V_CTRL_RESET (0x16)
#define AXP209_IRQ_BANK_1_CTRL_RESET (0xd8)
/* A simple I2C slave which returns values of ID or CNT register. */
typedef struct AXP209I2CState {
/*< private >*/
I2CSlave i2c;
/*< public >*/
uint8_t regs[NR_REGS]; /* peripheral registers */
uint8_t ptr; /* current register index */
uint8_t count; /* counter used for tx/rx */
} AXP209I2CState;
/* Reset all counters and load ID register */
static void axp209_reset_enter(Object *obj, ResetType type)
{
AXP209I2CState *s = AXP209(obj);
memset(s->regs, 0, NR_REGS);
s->ptr = 0;
s->count = 0;
s->regs[REG_CHIP_VERSION] = AXP209_CHIP_VERSION_ID;
s->regs[REG_DC_DC2_OUT_V_CTRL] = AXP209_DC_DC2_OUT_V_CTRL_RESET;
s->regs[REG_IRQ_BANK_1_CTRL] = AXP209_IRQ_BANK_1_CTRL_RESET;
}
/* Handle events from master. */
static int axp209_event(I2CSlave *i2c, enum i2c_event event)
{
AXP209I2CState *s = AXP209(i2c);
s->count = 0;
return 0;
}
/* Called when master requests read */
static uint8_t axp209_rx(I2CSlave *i2c)
{
AXP209I2CState *s = AXP209(i2c);
uint8_t ret = 0xff;
if (s->ptr < NR_REGS) {
ret = s->regs[s->ptr++];
}
trace_axp209_rx(s->ptr - 1, ret);
return ret;
}
/*
* Called when master sends write.
* Update ptr with byte 0, then perform write with second byte.
*/
static int axp209_tx(I2CSlave *i2c, uint8_t data)
{
AXP209I2CState *s = AXP209(i2c);
if (s->count == 0) {
/* Store register address */
s->ptr = data;
s->count++;
trace_axp209_select(data);
} else {
trace_axp209_tx(s->ptr, data);
if (s->ptr == REG_DC_DC2_OUT_V_CTRL) {
s->regs[s->ptr++] = data;
}
}
return 0;
}
static const VMStateDescription vmstate_axp209 = {
.name = TYPE_AXP209_PMU,
.version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY(regs, AXP209I2CState, NR_REGS),
VMSTATE_UINT8(count, AXP209I2CState),
VMSTATE_UINT8(ptr, AXP209I2CState),
VMSTATE_END_OF_LIST()
}
};
static void axp209_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
rc->phases.enter = axp209_reset_enter;
dc->vmsd = &vmstate_axp209;
isc->event = axp209_event;
isc->recv = axp209_rx;
isc->send = axp209_tx;
}
static const TypeInfo axp209_info = {
.name = TYPE_AXP209_PMU,
.parent = TYPE_I2C_SLAVE,
.instance_size = sizeof(AXP209I2CState),
.class_init = axp209_class_init
};
static void axp209_register_devices(void)
{
type_register_static(&axp209_info);
}
type_init(axp209_register_devices);

3
hw/misc/meson.build
View File

@ -38,11 +38,14 @@ subdir('macio')
softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c'))
softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c'))
softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_DRAMC', if_true: files('allwinner-a10-dramc.c'))
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c'))
specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'))
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-sysctrl.c'))
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.c'))
softmmu_ss.add(when: 'CONFIG_AXP209_PMU', if_true: files('axp209.c'))
softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c'))
softmmu_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c'))

12
hw/misc/omap_gpmc.c
View File

@ -126,7 +126,7 @@ static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value)
static uint64_t omap_nand_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
struct omap_gpmc_cs_file_s *f = opaque;
uint64_t v;
nand_setpins(f->dev, 0, 0, 0, 1, 0);
switch (omap_gpmc_devsize(f)) {
@ -205,7 +205,7 @@ static void omap_nand_setio(DeviceState *dev, uint64_t value,
static void omap_nand_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
struct omap_gpmc_cs_file_s *f = opaque;
nand_setpins(f->dev, 0, 0, 0, 1, 0);
omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
}
@ -290,7 +290,7 @@ static void fill_prefetch_fifo(struct omap_gpmc_s *s)
static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
struct omap_gpmc_s *s = opaque;
uint32_t data;
if (s->prefetch.config1 & 1) {
/* The TRM doesn't define the behaviour if you read from the
@ -320,7 +320,7 @@ static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
struct omap_gpmc_s *s = opaque;
int cs = prefetch_cs(s->prefetch.config1);
if ((s->prefetch.config1 & 1) == 0) {
/* The TRM doesn't define the behaviour of writing to the
@ -509,7 +509,7 @@ static int gpmc_wordaccess_only(hwaddr addr)
static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
struct omap_gpmc_s *s = opaque;
int cs;
struct omap_gpmc_cs_file_s *f;
@ -621,7 +621,7 @@ static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
static void omap_gpmc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
struct omap_gpmc_s *s = opaque;
int cs;
struct omap_gpmc_cs_file_s *f;

7
hw/misc/omap_l4.c
View File

@ -52,10 +52,9 @@ hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
return ta->start[region].size;
}
static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
struct omap_target_agent_s *s = opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
@ -79,7 +78,7 @@ static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
static void omap_l4ta_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
struct omap_target_agent_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);

7
hw/misc/omap_sdrc.c
View File

@ -31,10 +31,9 @@ void omap_sdrc_reset(struct omap_sdrc_s *s)
s->config = 0x10;
}
static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_sdrc_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
struct omap_sdrc_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);
@ -89,7 +88,7 @@ static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
static void omap_sdrc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
struct omap_sdrc_s *s = opaque;
if (size != 4) {
omap_badwidth_write32(opaque, addr, value);

5
hw/misc/omap_tap.c
View File

@ -23,10 +23,9 @@
#include "hw/arm/omap.h"
/* TEST-Chip-level TAP */
static uint64_t omap_tap_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
struct omap_mpu_state_s *s = opaque;
if (size != 4) {
return omap_badwidth_read32(opaque, addr);

12
hw/misc/sbsa_ec.c
View File

@ -15,13 +15,13 @@
#include "hw/sysbus.h"
#include "sysemu/runstate.h"
typedef struct {
typedef struct SECUREECState {
SysBusDevice parent_obj;
MemoryRegion iomem;
} SECUREECState;
#define TYPE_SBSA_EC "sbsa-ec"
#define SECURE_EC(obj) OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_EC)
#define TYPE_SBSA_SECURE_EC "sbsa-ec"
OBJECT_DECLARE_SIMPLE_TYPE(SECUREECState, SBSA_SECURE_EC)
enum sbsa_ec_powerstates {
SBSA_EC_CMD_POWEROFF = 0x01,
@ -36,7 +36,7 @@ static uint64_t sbsa_ec_read(void *opaque, hwaddr offset, unsigned size)
}
static void sbsa_ec_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
uint64_t value, unsigned size)
{
if (offset == 0) { /* PSCI machine power command register */
switch (value) {
@ -65,7 +65,7 @@ static const MemoryRegionOps sbsa_ec_ops = {
static void sbsa_ec_init(Object *obj)
{
SECUREECState *s = SECURE_EC(obj);
SECUREECState *s = SBSA_SECURE_EC(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &sbsa_ec_ops, s, "sbsa-ec",
@ -82,7 +82,7 @@ static void sbsa_ec_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo sbsa_ec_info = {
.name = TYPE_SBSA_EC,
.name = TYPE_SBSA_SECURE_EC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SECUREECState),
.instance_init = sbsa_ec_init,

5
hw/misc/trace-events
View File

@ -23,6 +23,11 @@ allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%"
avr_power_read(uint8_t value) "power_reduc read value:%u"
avr_power_write(uint8_t value) "power_reduc write value:%u"
# axp209.c
axp209_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
axp209_select(uint8_t reg) "Accessing reg 0x%" PRIx8
axp209_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
# eccmemctl.c
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"

9
hw/sd/omap_mmc.c
View File

@ -321,11 +321,10 @@ void omap_mmc_reset(struct omap_mmc_s *host)
device_cold_reset(DEVICE(host->card));
}
static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
unsigned size)
static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size)
{
uint16_t i;
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
struct omap_mmc_s *s = opaque;
if (size != 2) {
return omap_badwidth_read16(opaque, offset);
@ -418,7 +417,7 @@ static void omap_mmc_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
int i;
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
struct omap_mmc_s *s = opaque;
if (size != 2) {
omap_badwidth_write16(opaque, offset, value);
@ -576,7 +575,7 @@ static const MemoryRegionOps omap_mmc_ops = {
static void omap_mmc_cover_cb(void *opaque, int line, int level)
{
struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
struct omap_mmc_s *host = opaque;
if (!host->cdet_state && level) {
host->status |= 0x0002;

7
hw/ssi/omap_spi.c
View File

@ -134,10 +134,9 @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
omap_mcspi_interrupt_update(s);
}
static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
unsigned size)
static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
struct omap_mcspi_s *s = opaque;
int ch = 0;
uint32_t ret;
@ -226,7 +225,7 @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
static void omap_mcspi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
struct omap_mcspi_s *s = opaque;
int ch = 0;
if (size != 4) {

22
hw/timer/omap_gptimer.c
View File

@ -159,7 +159,7 @@ static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
static void omap_gp_timer_tick(void *opaque)
{
struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
struct omap_gp_timer_s *timer = opaque;
if (!timer->ar) {
timer->st = 0;
@ -179,7 +179,7 @@ static void omap_gp_timer_tick(void *opaque)
static void omap_gp_timer_match(void *opaque)
{
struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
struct omap_gp_timer_s *timer = opaque;
if (timer->trigger == gpt_trigger_both)
omap_gp_timer_trigger(timer);
@ -189,7 +189,7 @@ static void omap_gp_timer_match(void *opaque)
static void omap_gp_timer_input(void *opaque, int line, int on)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
struct omap_gp_timer_s *s = opaque;
int trigger;
switch (s->capture) {
@ -219,7 +219,7 @@ static void omap_gp_timer_input(void *opaque, int line, int on)
static void omap_gp_timer_clk_update(void *opaque, int line, int on)
{
struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
struct omap_gp_timer_s *timer = opaque;
omap_gp_timer_sync(timer);
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
@ -262,7 +262,7 @@ void omap_gp_timer_reset(struct omap_gp_timer_s *s)
static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
struct omap_gp_timer_s *s = opaque;
switch (addr) {
case 0x00: /* TIDR */
@ -328,7 +328,7 @@ static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
struct omap_gp_timer_s *s = opaque;
uint32_t ret;
if (addr & 2)
@ -340,10 +340,9 @@ static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
}
}
static void omap_gp_timer_write(void *opaque, hwaddr addr,
uint32_t value)
static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
struct omap_gp_timer_s *s = opaque;
switch (addr) {
case 0x00: /* TIDR */
@ -440,10 +439,9 @@ static void omap_gp_timer_write(void *opaque, hwaddr addr,
}
}
static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
uint32_t value)
static void omap_gp_timer_writeh(void *opaque, hwaddr addr, uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
struct omap_gp_timer_s *s = opaque;
if (addr & 2)
omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);

4
hw/timer/omap_synctimer.c
View File

@ -39,7 +39,7 @@ void omap_synctimer_reset(struct omap_synctimer_s *s)
static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
struct omap_synctimer_s *s = opaque;
switch (addr) {
case 0x00: /* 32KSYNCNT_REV */
@ -55,7 +55,7 @@ static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
struct omap_synctimer_s *s = opaque;
uint32_t ret;
if (addr & 2)

27
hw/timer/xilinx_timer.c
View File

@ -62,10 +62,10 @@ struct xlx_timer
};
#define TYPE_XILINX_TIMER "xlnx.xps-timer"
DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
TYPE_XILINX_TIMER)
typedef struct XpsTimerState XpsTimerState;
DECLARE_INSTANCE_CHECKER(XpsTimerState, XILINX_TIMER, TYPE_XILINX_TIMER)
struct timerblock
struct XpsTimerState
{
SysBusDevice parent_obj;
@ -76,7 +76,7 @@ struct timerblock
struct xlx_timer *timers;
};
static inline unsigned int num_timers(struct timerblock *t)
static inline unsigned int num_timers(XpsTimerState *t)
{
return 2 - t->one_timer_only;
}
@ -87,7 +87,7 @@ static inline unsigned int timer_from_addr(hwaddr addr)
return addr >> 2;
}
static void timer_update_irq(struct timerblock *t)
static void timer_update_irq(XpsTimerState *t)
{
unsigned int i, irq = 0;
uint32_t csr;
@ -104,7 +104,7 @@ static void timer_update_irq(struct timerblock *t)
static uint64_t
timer_read(void *opaque, hwaddr addr, unsigned int size)
{
struct timerblock *t = opaque;
XpsTimerState *t = opaque;
struct xlx_timer *xt;
uint32_t r = 0;
unsigned int timer;
@ -155,7 +155,7 @@ static void
timer_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct timerblock *t = opaque;
XpsTimerState *t = opaque;
struct xlx_timer *xt;
unsigned int timer;
uint32_t value = val64;
@ -202,7 +202,7 @@ static const MemoryRegionOps timer_ops = {
static void timer_hit(void *opaque)
{
struct xlx_timer *xt = opaque;
struct timerblock *t = xt->parent;
XpsTimerState *t = xt->parent;
D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
xt->regs[R_TCSR] |= TCSR_TINT;
@ -213,7 +213,7 @@ static void timer_hit(void *opaque)
static void xilinx_timer_realize(DeviceState *dev, Error **errp)
{
struct timerblock *t = XILINX_TIMER(dev);
XpsTimerState *t = XILINX_TIMER(dev);
unsigned int i;
/* Init all the ptimers. */
@ -236,16 +236,15 @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
static void xilinx_timer_init(Object *obj)
{
struct timerblock *t = XILINX_TIMER(obj);
XpsTimerState *t = XILINX_TIMER(obj);
/* All timers share a single irq line. */
sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
}
static Property xilinx_timer_properties[] = {
DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
62 * 1000000),
DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
DEFINE_PROP_END_OF_LIST(),
};
@ -260,7 +259,7 @@ static void xilinx_timer_class_init(ObjectClass *klass, void *data)
static const TypeInfo xilinx_timer_info = {
.name = TYPE_XILINX_TIMER,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(struct timerblock),
.instance_size = sizeof(XpsTimerState),
.instance_init = xilinx_timer_init,
.class_init = xilinx_timer_class_init,
};

7
include/hw/adc/npcm7xx_adc.h
View File

@ -42,7 +42,7 @@
* @iref: The internal reference voltage, initialized at launch time.
* @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
*/
typedef struct {
struct NPCM7xxADCState {
SysBusDevice parent;
MemoryRegion iomem;
@ -60,10 +60,9 @@ typedef struct {
uint32_t iref;
uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
} NPCM7xxADCState;
};
#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
#define NPCM7XX_ADC(obj) \
OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxADCState, NPCM7XX_ADC)
#endif /* NPCM7XX_ADC_H */

27
include/hw/arm/allwinner-a10.h
View File

@ -13,6 +13,10 @@
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/rtc/allwinner-rtc.h"
#include "hw/misc/allwinner-a10-ccm.h"
#include "hw/misc/allwinner-a10-dramc.h"
#include "hw/i2c/allwinner-i2c.h"
#include "sysemu/block-backend.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
@ -31,15 +35,38 @@ struct AwA10State {
/*< public >*/
ARMCPU cpu;
AwA10ClockCtlState ccm;
AwA10DramControllerState dramc;
AwA10PITState timer;
AwA10PICState intc;
AwEmacState emac;
AllwinnerAHCIState sata;
AwSdHostState mmc0;
AWI2CState i2c0;
AwRtcState rtc;
MemoryRegion sram_a;
EHCISysBusState ehci[AW_A10_NUM_USB];
OHCISysBusState ohci[AW_A10_NUM_USB];
};
/**
* Emulate Boot ROM firmware setup functionality.
*
* A real Allwinner A10 SoC contains a Boot ROM
* which is the first code that runs right after
* the SoC is powered on. The Boot ROM is responsible
* for loading user code (e.g. a bootloader) from any
* of the supported external devices and writing the
* downloaded code to internal SRAM. After loading the SoC
* begins executing the code written to SRAM.
*
* This function emulates the Boot ROM by copying 32 KiB
* of data at offset 8 KiB from the given block device and writes it to
* the start of the first internal SRAM memory.
*
* @s: Allwinner A10 state object pointer
* @blk: Block backend device object pointer
*/
void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk);
#endif

3
include/hw/arm/allwinner-h3.h
View File

@ -47,6 +47,7 @@
#include "hw/sd/allwinner-sdhost.h"
#include "hw/net/allwinner-sun8i-emac.h"
#include "hw/rtc/allwinner-rtc.h"
#include "hw/i2c/allwinner-i2c.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
@ -82,6 +83,7 @@ enum {
AW_H3_DEV_UART2,
AW_H3_DEV_UART3,
AW_H3_DEV_EMAC,
AW_H3_DEV_TWI0,
AW_H3_DEV_DRAMCOM,
AW_H3_DEV_DRAMCTL,
AW_H3_DEV_DRAMPHY,
@ -130,6 +132,7 @@ struct AwH3State {
AwH3SysCtrlState sysctrl;
AwSidState sid;
AwSdHostState mmc0;
AWI2CState i2c0;
AwSun8iEmacState emac;
AwRtcState rtc;
GICState gic;

18
include/hw/arm/npcm7xx.h
View File

@ -52,7 +52,7 @@
#define NPCM7XX_NR_PWM_MODULES 2
typedef struct NPCM7xxMachine {
struct NPCM7xxMachine {
MachineState parent;
/*
* PWM fan splitter. each splitter connects to one PWM output and
@ -60,11 +60,10 @@ typedef struct NPCM7xxMachine {
*/
SplitIRQ fan_splitter[NPCM7XX_NR_PWM_MODULES *
NPCM7XX_PWM_PER_MODULE];
} NPCM7xxMachine;
};
#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
#define NPCM7XX_MACHINE(obj) \
OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMachine, NPCM7XX_MACHINE)
typedef struct NPCM7xxMachineClass {
MachineClass parent;
@ -77,7 +76,7 @@ typedef struct NPCM7xxMachineClass {
#define NPCM7XX_MACHINE_GET_CLASS(obj) \
OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
typedef struct NPCM7xxState {
struct NPCM7xxState {
DeviceState parent;
ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS];
@ -105,10 +104,10 @@ typedef struct NPCM7xxState {
NPCM7xxFIUState fiu[2];
NPCM7xxEMCState emc[2];
NPCM7xxSDHCIState mmc;
} NPCM7xxState;
};
#define TYPE_NPCM7XX "npcm7xx"
#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
OBJECT_DECLARE_TYPE(NPCM7xxState, NPCM7xxClass, NPCM7XX)
#define TYPE_NPCM730 "npcm730"
#define TYPE_NPCM750 "npcm750"
@ -122,11 +121,6 @@ typedef struct NPCM7xxClass {
uint32_t num_cpus;
} NPCM7xxClass;
#define NPCM7XX_CLASS(klass) \
OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
#define NPCM7XX_GET_CLASS(obj) \
OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
/**
* npcm7xx_load_kernel - Loads memory with everything needed to boot
* @machine - The machine containing the SoC to be booted.

24
include/hw/arm/omap.h
View File

@ -70,9 +70,8 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
/* omap_intc.c */
#define TYPE_OMAP_INTC "common-omap-intc"
typedef struct omap_intr_handler_s omap_intr_handler;
DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
TYPE_OMAP_INTC)
typedef struct OMAPIntcState OMAPIntcState;
DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC)
/*
@ -89,8 +88,8 @@ DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
* (ie the struct omap_mpu_state_s*) to do the clockname to pointer
* translation.)
*/
void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk);
void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk);
void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk);
/* omap_i2c.c */
#define TYPE_OMAP_I2C "omap_i2c"
@ -103,21 +102,20 @@ void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
/* omap_gpio.c */
#define TYPE_OMAP1_GPIO "omap-gpio"
DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO,
typedef struct Omap1GpioState Omap1GpioState;
DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
TYPE_OMAP1_GPIO)
#define TYPE_OMAP2_GPIO "omap2-gpio"
DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
typedef struct Omap2GpioState Omap2GpioState;
DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO,
TYPE_OMAP2_GPIO)
typedef struct omap_gpif_s omap_gpif;
typedef struct omap2_gpif_s omap2_gpif;
/* TODO: clock framework (see above) */
void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk);
void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk);
void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk);
/* OMAP2 l4 Interconnect */
struct omap_l4_s;

11
include/hw/arm/pxa.h
View File

@ -119,14 +119,14 @@ void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
const struct keymap *map, int size);
/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
qemu_irq irq, uint32_t page_size);
I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
typedef struct PXA2xxI2SState PXA2xxI2SState;
OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
#define TYPE_PXA2XX_FIR "pxa2xx-fir"
OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR)
@ -193,8 +193,7 @@ struct PXA2xxI2SState {
# define PA_FMT "0x%08lx"
PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
const char *revision);
PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
PXA2xxState *pxa255_init(unsigned int sdram_size);
#endif /* PXA_H */

5
include/hw/arm/stm32f405_soc.h
View File

@ -46,7 +46,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
#define FLASH_BASE_ADDRESS 0x08000000
#define FLASH_SIZE (1024 * 1024)
#define SRAM_BASE_ADDRESS 0x20000000
#define SRAM_SIZE (192 * 1024)
#define SRAM_SIZE (128 * 1024)
#define CCM_BASE_ADDRESS 0x10000000
#define CCM_SIZE (64 * 1024)
struct STM32F405State {
/*< private >*/
@ -65,6 +67,7 @@ struct STM32F405State {
STM32F2XXADCState adc[STM_NUM_ADCS];
STM32F2XXSPIState spi[STM_NUM_SPIS];
MemoryRegion ccm;
MemoryRegion sram;
MemoryRegion flash;
MemoryRegion flash_alias;

55
include/hw/i2c/allwinner-i2c.h Normal file
View File

@ -0,0 +1,55 @@
/*
* Allwinner I2C Bus Serial Interface registers definition
*
* Copyright (C) 2022 Strahinja Jankovic. <strahinja.p.jankovic@gmail.com>
*
* This file is derived from IMX I2C controller,
* by Jean-Christophe DUBOIS .
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef ALLWINNER_I2C_H
#define ALLWINNER_I2C_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_AW_I2C "allwinner.i2c"
OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
#define AW_I2C_MEM_SIZE 0x24
struct AWI2CState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
I2CBus *bus;
qemu_irq irq;
uint8_t addr;
uint8_t xaddr;
uint8_t data;
uint8_t cntr;
uint8_t stat;
uint8_t ccr;
uint8_t srst;
uint8_t efr;
uint8_t lcr;
};
#endif /* ALLWINNER_I2C_H */

7
include/hw/i2c/npcm7xx_smbus.h
View File

@ -68,7 +68,7 @@ typedef enum NPCM7xxSMBusStatus {
* @rx_cur: The current position of rx_fifo.
* @status: The current status of the SMBus.
*/
typedef struct NPCM7xxSMBusState {
struct NPCM7xxSMBusState {
SysBusDevice parent;
MemoryRegion iomem;
@ -104,10 +104,9 @@ typedef struct NPCM7xxSMBusState {
uint8_t rx_cur;
NPCM7xxSMBusStatus status;
} NPCM7xxSMBusState;
};
#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \
TYPE_NPCM7XX_SMBUS)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSMBusState, NPCM7XX_SMBUS)
#endif /* NPCM7XX_SMBUS_H */

67
include/hw/misc/allwinner-a10-ccm.h Normal file
View File

@ -0,0 +1,67 @@
/*
* Allwinner A10 Clock Control Module emulation
*
* Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
*
* This file is derived from Allwinner H3 CCU,
* by Niek Linnenbank.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_MISC_ALLWINNER_A10_CCM_H
#define HW_MISC_ALLWINNER_A10_CCM_H
#include "qom/object.h"
#include "hw/sysbus.h"
/**
* @name Constants
* @{
*/
/** Size of register I/O address space used by CCM device */
#define AW_A10_CCM_IOSIZE (0x400)
/** Total number of known registers */
#define AW_A10_CCM_REGS_NUM (AW_A10_CCM_IOSIZE / sizeof(uint32_t))
/** @} */
/**
* @name Object model
* @{
*/
#define TYPE_AW_A10_CCM "allwinner-a10-ccm"
OBJECT_DECLARE_SIMPLE_TYPE(AwA10ClockCtlState, AW_A10_CCM)
/** @} */
/**
* Allwinner A10 CCM object instance state.
*/
struct AwA10ClockCtlState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
/** Maps I/O registers in physical memory */
MemoryRegion iomem;
/** Array of hardware registers */
uint32_t regs[AW_A10_CCM_REGS_NUM];
};
#endif /* HW_MISC_ALLWINNER_H3_CCU_H */

68
include/hw/misc/allwinner-a10-dramc.h Normal file
View File

@ -0,0 +1,68 @@
/*
* Allwinner A10 DRAM Controller emulation
*
* Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
*
* This file is derived from Allwinner H3 DRAMC,
* by Niek Linnenbank.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_MISC_ALLWINNER_A10_DRAMC_H
#define HW_MISC_ALLWINNER_A10_DRAMC_H
#include "qom/object.h"
#include "hw/sysbus.h"
#include "hw/register.h"
/**
* @name Constants
* @{
*/
/** Size of register I/O address space used by DRAMC device */
#define AW_A10_DRAMC_IOSIZE (0x1000)
/** Total number of known registers */
#define AW_A10_DRAMC_REGS_NUM (AW_A10_DRAMC_IOSIZE / sizeof(uint32_t))
/** @} */
/**
* @name Object model
* @{
*/
#define TYPE_AW_A10_DRAMC "allwinner-a10-dramc"
OBJECT_DECLARE_SIMPLE_TYPE(AwA10DramControllerState, AW_A10_DRAMC)
/** @} */
/**
* Allwinner A10 DRAMC object instance state.
*/
struct AwA10DramControllerState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
/** Maps I/O registers in physical memory */
MemoryRegion iomem;
/** Array of hardware registers */
uint32_t regs[AW_A10_DRAMC_REGS_NUM];
};
#endif /* HW_MISC_ALLWINNER_A10_DRAMC_H */

2
include/hw/misc/npcm7xx_clk.h
View File

@ -175,6 +175,6 @@ struct NPCM7xxCLKState {
};
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
#endif /* NPCM7XX_CLK_H */

6
include/hw/misc/npcm7xx_gcr.h
View File

@ -55,7 +55,7 @@
*/
#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
typedef struct NPCM7xxGCRState {
struct NPCM7xxGCRState {
SysBusDevice parent;
MemoryRegion iomem;
@ -65,9 +65,9 @@ typedef struct NPCM7xxGCRState {
uint32_t reset_pwron;
uint32_t reset_mdlr;
uint32_t reset_intcr3;
} NPCM7xxGCRState;
};
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR)
#endif /* NPCM7XX_GCR_H */

7
include/hw/misc/npcm7xx_mft.h
View File

@ -49,7 +49,7 @@
* @max_rpm: The maximum rpm for fans. Order: A0, B0, A1, B1.
* @duty: The duty cycles for fans, relative to NPCM7XX_PWM_MAX_DUTY.
*/
typedef struct NPCM7xxMFTState {
struct NPCM7xxMFTState {
SysBusDevice parent;
MemoryRegion iomem;
@ -61,10 +61,9 @@ typedef struct NPCM7xxMFTState {
uint32_t max_rpm[NPCM7XX_MFT_FANIN_COUNT];
uint32_t duty[NPCM7XX_MFT_FANIN_COUNT];
} NPCM7xxMFTState;
};
#define TYPE_NPCM7XX_MFT "npcm7xx-mft"
#define NPCM7XX_MFT(obj) \
OBJECT_CHECK(NPCM7xxMFTState, (obj), TYPE_NPCM7XX_MFT)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMFTState, NPCM7XX_MFT)
#endif /* NPCM7XX_MFT_H */

3
include/hw/misc/npcm7xx_pwm.h
View File

@ -101,7 +101,6 @@ struct NPCM7xxPWMState {
};
#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
#define NPCM7XX_PWM(obj) \
OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxPWMState, NPCM7XX_PWM)
#endif /* NPCM7XX_PWM_H */

6
include/hw/misc/npcm7xx_rng.h
View File

@ -18,7 +18,7 @@
#include "hw/sysbus.h"
typedef struct NPCM7xxRNGState {
struct NPCM7xxRNGState {
SysBusDevice parent;
MemoryRegion iomem;
@ -26,9 +26,9 @@ typedef struct NPCM7xxRNGState {
uint8_t rngcs;
uint8_t rngd;
uint8_t rngmode;
} NPCM7xxRNGState;
};
#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxRNGState, NPCM7XX_RNG)
#endif /* NPCM7XX_RNG_H */

5
include/hw/net/npcm7xx_emc.h
View File

@ -277,10 +277,7 @@ struct NPCM7xxEMCState {
bool rx_active;
};
typedef struct NPCM7xxEMCState NPCM7xxEMCState;
#define TYPE_NPCM7XX_EMC "npcm7xx-emc"
#define NPCM7XX_EMC(obj) \
OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxEMCState, NPCM7XX_EMC)
#endif /* NPCM7XX_EMC_H */

4
include/hw/sd/npcm7xx_sdhci.h
View File

@ -51,7 +51,7 @@ typedef struct NPCM7xxRegs {
uint32_t boottoctrl;
} NPCM7xxRegisters;
typedef struct NPCM7xxSDHCIState {
struct NPCM7xxSDHCIState {
SysBusDevice parent;
MemoryRegion container;
@ -60,6 +60,6 @@ typedef struct NPCM7xxSDHCIState {
NPCM7xxRegisters regs;
SDHCIState sdhci;
} NPCM7xxSDHCIState;
};
#endif /* NPCM7XX_SDHCI_H */

3
target/arm/helper.c
View File

@ -1866,6 +1866,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
if (cpu_isar_feature(aa64_sme, cpu)) {
valid_mask |= SCR_ENTP2;
}
if (cpu_isar_feature(aa64_hcx, cpu)) {
valid_mask |= SCR_HXEN;
}
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
if (cpu_isar_feature(aa32_ras, cpu)) {

14
target/arm/sve_helper.c
View File

@ -5354,15 +5354,10 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
#ifdef CONFIG_USER_ONLY
flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
&info->host, retaddr);
memset(&info->attrs, 0, sizeof(info->attrs));
/* Require both ANON and MTE; see allocation_tag_mem(). */
info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
#else
CPUTLBEntryFull *full;
flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
&info->host, &full, retaddr);
info->attrs = full->attrs;
info->tagged = full->pte_attrs == 0xf0;
#endif
info->flags = flags;
@ -5371,6 +5366,15 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
return false;
}
#ifdef CONFIG_USER_ONLY
memset(&info->attrs, 0, sizeof(info->attrs));
/* Require both ANON and MTE; see allocation_tag_mem(). */
info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
#else
info->attrs = full->attrs;
info->tagged = full->pte_attrs == 0xf0;
#endif
/* Ensure that info->host[] is relative to addr, not addr + mem_off. */
info->host -= mem_off;
return true;

47
tests/avocado/boot_linux_console.py
View File

@ -620,6 +620,53 @@ class BootLinuxConsole(LinuxKernelTest):
'sda')
# cubieboard's reboot is not functioning; omit reboot test.
@skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
def test_arm_cubieboard_openwrt_22_03_2(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:cubieboard
:avocado: tags=device:sd
"""
# This test download a 7.5 MiB compressed image and expand it
# to 126 MiB.
image_url = ('https://downloads.openwrt.org/releases/22.03.2/targets/'
'sunxi/cortexa8/openwrt-22.03.2-sunxi-cortexa8-'
'cubietech_a10-cubieboard-ext4-sdcard.img.gz')
image_hash = ('94b5ecbfbc0b3b56276e5146b899eafa'
'2ac5dc2d08733d6705af9f144f39f554')
image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
image_path = archive.extract(image_path_gz, self.workdir)
image_pow2ceil_expand(image_path)
self.vm.set_console()
self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
'-nic', 'user',
'-no-reboot')
self.vm.launch()
kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
'usbcore.nousb '
'noreboot')
self.wait_for_console_pattern('U-Boot SPL')
interrupt_interactive_console_until_pattern(
self, 'Hit any key to stop autoboot:', '=>')
exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
kernel_command_line + "'", '=>')
exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
self.wait_for_console_pattern(
'Please press Enter to activate this console.')
exec_command_and_wait_for_pattern(self, ' ', 'root@')
exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
'Allwinner sun4i/sun5i')
# cubieboard's reboot is not functioning; omit reboot test.
@skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
def test_arm_quanta_gsj(self):
"""