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trivial patches for 2024-03-09

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Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging

trivial patches for 2024-03-09

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# gpg: Signature made Sat 09 Mar 2024 15:57:06 GMT
# gpg:                using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59
# gpg:                issuer "mjt@tls.msk.ru"
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@debian.org>" [full]
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D  4324 457C E0A0 8044 65C5
#      Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931  4B22 701B 4F6B 1A69 3E59

* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu:
  docs/acpi/bits: add some clarity and details while also improving formating
  hw/mem/cxl_type3: Fix problem with g_steal_pointer()
  hw/pci-bridge/cxl_upstream: Fix problem with g_steal_pointer()
  hw/cxl/cxl-cdat: Fix type of buf in ct3_load_cdat()
  qerror: QERR_DEVICE_IN_USE is no longer used, drop
  blockdev: Fix block_resize error reporting for op blockers
  char: Slightly better error reporting when chardev is in use
  make-release: switch to .xz format by default
  hw/scsi/lsi53c895a: Fix typo in comment
  hw/vfio/pci.c: Make some structure static
  replay: Improve error messages about configuration conflicts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-03-09 20:12:05 +00:00
commit 89126b6dca
13 changed files with 82 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
blockdev.c
View File

@ -2252,8 +2252,7 @@ void coroutine_fn qmp_block_resize(const char *device, const char *node_name,
} }
bdrv_graph_co_rdlock(); bdrv_graph_co_rdlock();
if (bdrv_op_is_blocked(bs, BLOCK_OP_TYPE_RESIZE, NULL)) { if (bdrv_op_is_blocked(bs, BLOCK_OP_TYPE_RESIZE, errp)) {
error_setg(errp, QERR_DEVICE_IN_USE, device);
bdrv_graph_co_rdunlock(); bdrv_graph_co_rdunlock();
return; return;
} }

13
chardev/char-fe.c
View File

@ -199,13 +199,18 @@ bool qemu_chr_fe_init(CharBackend *b, Chardev *s, Error **errp)
MuxChardev *d = MUX_CHARDEV(s); MuxChardev *d = MUX_CHARDEV(s);
if (d->mux_cnt >= MAX_MUX) { if (d->mux_cnt >= MAX_MUX) {
goto unavailable; error_setg(errp,
"too many uses of multiplexed chardev '%s'"
" (maximum is " stringify(MAX_MUX) ")",
s->label);
return false;
} }
d->backends[d->mux_cnt] = b; d->backends[d->mux_cnt] = b;
tag = d->mux_cnt++; tag = d->mux_cnt++;
} else if (s->be) { } else if (s->be) {
goto unavailable; error_setg(errp, "chardev '%s' is already in use", s->label);
return false;
} else { } else {
s->be = b; s->be = b;
} }
@ -215,10 +220,6 @@ bool qemu_chr_fe_init(CharBackend *b, Chardev *s, Error **errp)
b->tag = tag; b->tag = tag;
b->chr = s; b->chr = s;
return true; return true;
unavailable:
error_setg(errp, QERR_DEVICE_IN_USE, s->label);
return false;
} }
void qemu_chr_fe_deinit(CharBackend *b, bool del) void qemu_chr_fe_deinit(CharBackend *b, bool del)

55
docs/devel/acpi-bits.rst
View File

@ -1,26 +1,48 @@
============================================================================= =============================================================================
ACPI/SMBIOS avocado tests using biosbits ACPI/SMBIOS avocado tests using biosbits
============================================================================= =============================================================================
************
Introduction
************
Biosbits is a software written by Josh Triplett that can be downloaded Biosbits is a software written by Josh Triplett that can be downloaded
from https://biosbits.org/. The github codebase can be found from https://biosbits.org/. The github codebase can be found
`here <https://github.com/biosbits/bits/tree/master>`__. It is a software that executes `here <https://github.com/biosbits/bits/tree/master>`__. It is a software that
the bios components such as acpi and smbios tables directly through acpica executes the bios components such as acpi and smbios tables directly through
bios interpreter (a freely available C based library written by Intel, acpica bios interpreter (a freely available C based library written by Intel,
downloadable from https://acpica.org/ and is included with biosbits) without an downloadable from https://acpica.org/ and is included with biosbits) without an
operating system getting involved in between. operating system getting involved in between. Bios-bits has python integration
with grub so actual routines that executes bios components can be written in
python instead of bash-ish (grub's native scripting language).
There are several advantages to directly testing the bios in a real physical There are several advantages to directly testing the bios in a real physical
machine or VM as opposed to indirectly discovering bios issues through the machine or in a VM as opposed to indirectly discovering bios issues through the
operating system. For one thing, the OSes tend to hide bios problems from the operating system (the OS). Operating systems tend to bypass bios problems and
end user. The other is that we have more control of what we wanted to test hide them from the end user. We have more control of what we wanted to test and
and how by directly using acpica interpreter on top of the bios on a running how by being as close to the bios on a running system as possible without a
system. More details on the inspiration for developing biosbits and its real complicated software component such as an operating system coming in between.
life uses can be found in [#a]_ and [#b]_. Another issue is that we cannot exercise bios components such as ACPI and
SMBIOS without being in the highest hardware privilege level, ring 0 for
example in case of x86. Since the OS executes from ring 0 whereas normal user
land software resides in unprivileged ring 3, operating system must be modified
in order to write our test routines that exercise and test the bios. This is
not possible in all cases. Lastly, test frameworks and routines are preferably
written using a high level scripting language such as python. OSes and
OS modules are generally written using low level languages such as C and
low level assembly machine language. Writing test routines in a low level
language makes things more cumbersome. These and other reasons makes using
bios-bits very attractive for testing bioses. More details on the inspiration
for developing biosbits and its real life uses can be found in [#a]_ and [#b]_.
For QEMU, we maintain a fork of bios bits in gitlab along with all the For QEMU, we maintain a fork of bios bits in gitlab along with all the
dependent submodules here: https://gitlab.com/qemu-project/biosbits-bits dependent submodules `here <https://gitlab.com/qemu-project/biosbits-bits>`__.
This fork contains numerous fixes, a newer acpica and changes specific to This fork contains numerous fixes, a newer acpica and changes specific to
running this avocado QEMU tests using bits. The author of this document running this avocado QEMU tests using bits. The author of this document
is the sole maintainer of the QEMU fork of bios bits repo. is the sole maintainer of the QEMU fork of bios bits repository. For more
information, please see author's `FOSDEM talk on this bios-bits based test
framework <https://fosdem.org/2024/schedule/event/fosdem-2024-2262-exercising-qemu-generated-acpi-smbios-tables-using-biosbits-from-within-a-guest-vm-/>`__.
*********************************
Description of the test framework
*********************************
Under the directory ``tests/avocado/``, ``acpi-bits.py`` is a QEMU avocado Under the directory ``tests/avocado/``, ``acpi-bits.py`` is a QEMU avocado
test that drives all this. test that drives all this.
@ -120,8 +142,9 @@ Under ``tests/avocado/`` as the root we have:
(b) Add a SPDX license header. (b) Add a SPDX license header.
(c) Perform modifications to the test. (c) Perform modifications to the test.
Commits (a), (b) and (c) should go under separate commits so that the original Commits (a), (b) and (c) preferably should go under separate commits so that
test script and the changes we have made are separated and clear. the original test script and the changes we have made are separated and
clear. (a) and (b) can sometimes be combined into a single step.
The test framework will then use your modified test script to run the test. The test framework will then use your modified test script to run the test.
No further changes would be needed. Please check the logs to make sure that No further changes would be needed. Please check the logs to make sure that
@ -141,4 +164,4 @@ References:
----------- -----------
.. [#a] https://blog.linuxplumbersconf.org/2011/ocw/system/presentations/867/original/bits.pdf .. [#a] https://blog.linuxplumbersconf.org/2011/ocw/system/presentations/867/original/bits.pdf
.. [#b] https://www.youtube.com/watch?v=36QIepyUuhg .. [#b] https://www.youtube.com/watch?v=36QIepyUuhg
.. [#c] https://fosdem.org/2024/schedule/event/fosdem-2024-2262-exercising-qemu-generated-acpi-smbios-tables-using-biosbits-from-within-a-guest-vm-/

4
hw/cxl/cxl-cdat.c
View File

@ -114,7 +114,7 @@ static void ct3_build_cdat(CDATObject *cdat, Error **errp)
static void ct3_load_cdat(CDATObject *cdat, Error **errp) static void ct3_load_cdat(CDATObject *cdat, Error **errp)
{ {
g_autofree CDATEntry *cdat_st = NULL; g_autofree CDATEntry *cdat_st = NULL;
g_autofree char *buf = NULL; g_autofree uint8_t *buf = NULL;
uint8_t sum = 0; uint8_t sum = 0;
int num_ent; int num_ent;
int i = 0, ent = 1; int i = 0, ent = 1;
@ -171,7 +171,7 @@ static void ct3_load_cdat(CDATObject *cdat, Error **errp)
cdat_st[ent].base = hdr; cdat_st[ent].base = hdr;
cdat_st[ent].length = hdr->length; cdat_st[ent].length = hdr->length;
while (buf + i < (char *)cdat_st[ent].base + cdat_st[ent].length) { while (buf + i < (uint8_t *)cdat_st[ent].base + cdat_st[ent].length) {
assert(i < file_size); assert(i < file_size);
sum += buf[i++]; sum += buf[i++];
} }

24
hw/mem/cxl_type3.c
View File

@ -46,12 +46,12 @@ static void ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
int dsmad_handle, MemoryRegion *mr, int dsmad_handle, MemoryRegion *mr,
bool is_pmem, uint64_t dpa_base) bool is_pmem, uint64_t dpa_base)
{ {
g_autofree CDATDsmas *dsmas = NULL; CDATDsmas *dsmas;
g_autofree CDATDslbis *dslbis0 = NULL; CDATDslbis *dslbis0;
g_autofree CDATDslbis *dslbis1 = NULL; CDATDslbis *dslbis1;
g_autofree CDATDslbis *dslbis2 = NULL; CDATDslbis *dslbis2;
g_autofree CDATDslbis *dslbis3 = NULL; CDATDslbis *dslbis3;
g_autofree CDATDsemts *dsemts = NULL; CDATDsemts *dsemts;
dsmas = g_malloc(sizeof(*dsmas)); dsmas = g_malloc(sizeof(*dsmas));
*dsmas = (CDATDsmas) { *dsmas = (CDATDsmas) {
@ -135,12 +135,12 @@ static void ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table,
}; };
/* Header always at start of structure */ /* Header always at start of structure */
cdat_table[CT3_CDAT_DSMAS] = g_steal_pointer(&dsmas); cdat_table[CT3_CDAT_DSMAS] = (CDATSubHeader *)dsmas;
cdat_table[CT3_CDAT_DSLBIS0] = g_steal_pointer(&dslbis0); cdat_table[CT3_CDAT_DSLBIS0] = (CDATSubHeader *)dslbis0;
cdat_table[CT3_CDAT_DSLBIS1] = g_steal_pointer(&dslbis1); cdat_table[CT3_CDAT_DSLBIS1] = (CDATSubHeader *)dslbis1;
cdat_table[CT3_CDAT_DSLBIS2] = g_steal_pointer(&dslbis2); cdat_table[CT3_CDAT_DSLBIS2] = (CDATSubHeader *)dslbis2;
cdat_table[CT3_CDAT_DSLBIS3] = g_steal_pointer(&dslbis3); cdat_table[CT3_CDAT_DSLBIS3] = (CDATSubHeader *)dslbis3;
cdat_table[CT3_CDAT_DSEMTS] = g_steal_pointer(&dsemts); cdat_table[CT3_CDAT_DSEMTS] = (CDATSubHeader *)dsemts;
} }
static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv)

8
hw/pci-bridge/cxl_upstream.c
View File

@ -192,8 +192,8 @@ enum {
static int build_cdat_table(CDATSubHeader ***cdat_table, void *priv) static int build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
{ {
g_autofree CDATSslbis *sslbis_latency = NULL; CDATSslbis *sslbis_latency;
g_autofree CDATSslbis *sslbis_bandwidth = NULL; CDATSslbis *sslbis_bandwidth;
CXLUpstreamPort *us = CXL_USP(priv); CXLUpstreamPort *us = CXL_USP(priv);
PCIBus *bus = &PCI_BRIDGE(us)->sec_bus; PCIBus *bus = &PCI_BRIDGE(us)->sec_bus;
int devfn, sslbis_size, i; int devfn, sslbis_size, i;
@ -270,8 +270,8 @@ static int build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
*cdat_table = g_new0(CDATSubHeader *, CXL_USP_CDAT_NUM_ENTRIES); *cdat_table = g_new0(CDATSubHeader *, CXL_USP_CDAT_NUM_ENTRIES);
/* Header always at start of structure */ /* Header always at start of structure */
(*cdat_table)[CXL_USP_CDAT_SSLBIS_LAT] = g_steal_pointer(&sslbis_latency); (*cdat_table)[CXL_USP_CDAT_SSLBIS_LAT] = (CDATSubHeader *)sslbis_latency;
(*cdat_table)[CXL_USP_CDAT_SSLBIS_BW] = g_steal_pointer(&sslbis_bandwidth); (*cdat_table)[CXL_USP_CDAT_SSLBIS_BW] = (CDATSubHeader *)sslbis_bandwidth;
return CXL_USP_CDAT_NUM_ENTRIES; return CXL_USP_CDAT_NUM_ENTRIES;
} }

2
hw/scsi/lsi53c895a.c
View File

@ -227,7 +227,7 @@ struct LSIState {
AddressSpace pci_io_as; AddressSpace pci_io_as;
QEMUTimer *scripts_timer; QEMUTimer *scripts_timer;
int carry; /* ??? Should this be an a visible register somewhere? */ int carry; /* ??? Should this be in a visible register somewhere? */
int status; int status;
int msg_action; int msg_action;
int msg_len; int msg_len;

4
hw/vfio/pci.c
View File

@ -2558,7 +2558,7 @@ static bool vfio_display_migration_needed(void *opaque)
(vdev->ramfb_migrate == ON_OFF_AUTO_AUTO && vdev->enable_ramfb); (vdev->ramfb_migrate == ON_OFF_AUTO_AUTO && vdev->enable_ramfb);
} }
const VMStateDescription vmstate_vfio_display = { static const VMStateDescription vmstate_vfio_display = {
.name = "VFIOPCIDevice/VFIODisplay", .name = "VFIOPCIDevice/VFIODisplay",
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
@ -2570,7 +2570,7 @@ const VMStateDescription vmstate_vfio_display = {
} }
}; };
const VMStateDescription vmstate_vfio_pci_config = { static const VMStateDescription vmstate_vfio_pci_config = {
.name = "VFIOPCIDevice", .name = "VFIOPCIDevice",
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,

17
include/hw/cxl/cxl_cdat.h
View File

@ -82,7 +82,8 @@ typedef struct CDATDsmas {
uint16_t reserved; uint16_t reserved;
uint64_t DPA_base; uint64_t DPA_base;
uint64_t DPA_length; uint64_t DPA_length;
} QEMU_PACKED CDATDsmas; } CDATDsmas;
QEMU_BUILD_BUG_ON(sizeof(CDATDsmas) != 24);
/* Device Scoped Latency and Bandwidth Information Structure - CDAT Table 5 */ /* Device Scoped Latency and Bandwidth Information Structure - CDAT Table 5 */
typedef struct CDATDslbis { typedef struct CDATDslbis {
@ -95,7 +96,8 @@ typedef struct CDATDslbis {
uint64_t entry_base_unit; uint64_t entry_base_unit;
uint16_t entry[3]; uint16_t entry[3];
uint16_t reserved2; uint16_t reserved2;
} QEMU_PACKED CDATDslbis; } CDATDslbis;
QEMU_BUILD_BUG_ON(sizeof(CDATDslbis) != 24);
/* Device Scoped Memory Side Cache Information Structure - CDAT Table 6 */ /* Device Scoped Memory Side Cache Information Structure - CDAT Table 6 */
typedef struct CDATDsmscis { typedef struct CDATDsmscis {
@ -122,7 +124,8 @@ typedef struct CDATDsemts {
uint16_t reserved; uint16_t reserved;
uint64_t DPA_offset; uint64_t DPA_offset;
uint64_t DPA_length; uint64_t DPA_length;
} QEMU_PACKED CDATDsemts; } CDATDsemts;
QEMU_BUILD_BUG_ON(sizeof(CDATDsemts) != 24);
/* Switch Scoped Latency and Bandwidth Information Structure - CDAT Table 9 */ /* Switch Scoped Latency and Bandwidth Information Structure - CDAT Table 9 */
typedef struct CDATSslbisHeader { typedef struct CDATSslbisHeader {
@ -130,7 +133,8 @@ typedef struct CDATSslbisHeader {
uint8_t data_type; uint8_t data_type;
uint8_t reserved[3]; uint8_t reserved[3];
uint64_t entry_base_unit; uint64_t entry_base_unit;
} QEMU_PACKED CDATSslbisHeader; } CDATSslbisHeader;
QEMU_BUILD_BUG_ON(sizeof(CDATSslbisHeader) != 16);
#define CDAT_PORT_ID_USP 0x100 #define CDAT_PORT_ID_USP 0x100
/* Switch Scoped Latency and Bandwidth Entry - CDAT Table 10 */ /* Switch Scoped Latency and Bandwidth Entry - CDAT Table 10 */
@ -139,12 +143,13 @@ typedef struct CDATSslbe {
uint16_t port_y_id; uint16_t port_y_id;
uint16_t latency_bandwidth; uint16_t latency_bandwidth;
uint16_t reserved; uint16_t reserved;
} QEMU_PACKED CDATSslbe; } CDATSslbe;
QEMU_BUILD_BUG_ON(sizeof(CDATSslbe) != 8);
typedef struct CDATSslbis { typedef struct CDATSslbis {
CDATSslbisHeader sslbis_header; CDATSslbisHeader sslbis_header;
CDATSslbe sslbe[]; CDATSslbe sslbe[];
} QEMU_PACKED CDATSslbis; } CDATSslbis;
typedef struct CDATEntry { typedef struct CDATEntry {
void *base; void *base;

3
include/qapi/qmp/qerror.h
View File

@ -23,9 +23,6 @@
#define QERR_DEVICE_HAS_NO_MEDIUM \ #define QERR_DEVICE_HAS_NO_MEDIUM \
"Device '%s' has no medium" "Device '%s' has no medium"
#define QERR_DEVICE_IN_USE \
"Device '%s' is in use"
#define QERR_DEVICE_NO_HOTPLUG \ #define QERR_DEVICE_NO_HOTPLUG \
"Device '%s' does not support hotplugging" "Device '%s' does not support hotplugging"

2
replay/replay.c
View File

@ -511,7 +511,7 @@ void replay_add_blocker(const char *feature)
{ {
Error *reason = NULL; Error *reason = NULL;
error_setg(&reason, "Record/replay feature is not supported for '%s'", error_setg(&reason, "Record/replay is not supported with %s",
feature); feature);
replay_blockers = g_slist_prepend(replay_blockers, reason); replay_blockers = g_slist_prepend(replay_blockers, reason);
} }

2
scripts/make-release
View File

@ -47,5 +47,5 @@ meson subprojects download $SUBPROJECTS
CryptoPkg/Library/OpensslLib/openssl \ CryptoPkg/Library/OpensslLib/openssl \
MdeModulePkg/Library/BrotliCustomDecompressLib/brotli) MdeModulePkg/Library/BrotliCustomDecompressLib/brotli)
popd popd
tar --exclude=.git -cjf ${destination}.tar.bz2 ${destination} tar --exclude=.git -cJf ${destination}.tar.xz ${destination}
rm -rf ${destination} rm -rf ${destination}

2
system/vl.c
View File

@ -1932,7 +1932,7 @@ static void qemu_apply_machine_options(QDict *qdict)
} }
if (current_machine->smp.cpus > 1) { if (current_machine->smp.cpus > 1) {
replay_add_blocker("smp"); replay_add_blocker("multiple CPUs");
} }
} }