more precise stack operations in call/int gates (16 bit wrapping is handled in all cases) - makes all call/int gates operations restartable in case of exception
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@462 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
7dea1da4ae
commit
891b38e446
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@ -531,16 +531,49 @@ void check_iol_DX(void)
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check_io(EDX & 0xffff, 4);
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}
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static inline unsigned int get_sp_mask(unsigned int e2)
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{
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if (e2 & DESC_B_MASK)
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return 0xffffffff;
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else
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return 0xffff;
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}
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/* XXX: add a is_user flag to have proper security support */
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#define PUSHW(ssp, sp, sp_mask, val)\
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{\
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sp -= 2;\
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stw_kernel((ssp) + (sp & (sp_mask)), (val));\
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}
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#define PUSHL(ssp, sp, sp_mask, val)\
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{\
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sp -= 4;\
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stl_kernel((ssp) + (sp & (sp_mask)), (val));\
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}
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#define POPW(ssp, sp, sp_mask, val)\
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{\
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val = lduw_kernel((ssp) + (sp & (sp_mask)));\
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sp += 2;\
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}
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#define POPL(ssp, sp, sp_mask, val)\
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{\
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val = ldl_kernel((ssp) + (sp & (sp_mask)));\
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sp += 4;\
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}
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/* protected mode interrupt */
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static void do_interrupt_protected(int intno, int is_int, int error_code,
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unsigned int next_eip, int is_hw)
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{
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SegmentCache *dt;
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uint8_t *ptr, *ssp;
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int type, dpl, selector, ss_dpl, cpl;
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int type, dpl, selector, ss_dpl, cpl, sp_mask;
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int has_error_code, new_stack, shift;
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uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2, push_size;
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uint32_t old_cs, old_ss, old_esp, old_eip;
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uint32_t e1, e2, offset, ss, esp, ss_e1, ss_e2;
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uint32_t old_eip;
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#ifdef DEBUG_PCALL
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if (loglevel) {
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@ -659,39 +692,72 @@ static void do_interrupt_protected(int intno, int is_int, int error_code,
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if (!(ss_e2 & DESC_P_MASK))
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raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
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new_stack = 1;
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sp_mask = get_sp_mask(ss_e2);
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ssp = get_seg_base(ss_e1, ss_e2);
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} else if ((e2 & DESC_C_MASK) || dpl == cpl) {
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/* to same priviledge */
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new_stack = 0;
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sp_mask = get_sp_mask(env->segs[R_SS].flags);
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ssp = env->segs[R_SS].base;
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esp = ESP;
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} else {
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raise_exception_err(EXCP0D_GPF, selector & 0xfffc);
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new_stack = 0; /* avoid warning */
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sp_mask = 0; /* avoid warning */
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ssp = NULL; /* avoid warning */
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esp = 0; /* avoid warning */
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}
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shift = type >> 3;
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#if 0
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/* XXX: check that enough room is available */
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push_size = 6 + (new_stack << 2) + (has_error_code << 1);
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if (env->eflags & VM_MASK)
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push_size += 8;
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push_size <<= shift;
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/* XXX: check that enough room is available */
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if (new_stack) {
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old_esp = ESP;
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old_ss = env->segs[R_SS].selector;
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ss = (ss & ~3) | dpl;
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cpu_x86_load_seg_cache(env, R_SS, ss,
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get_seg_base(ss_e1, ss_e2),
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get_seg_limit(ss_e1, ss_e2),
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ss_e2);
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} else {
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old_esp = 0;
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old_ss = 0;
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esp = ESP;
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}
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#endif
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if (is_int)
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old_eip = next_eip;
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else
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old_eip = env->eip;
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old_cs = env->segs[R_CS].selector;
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if (shift == 1) {
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if (env->eflags & VM_MASK) {
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PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
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PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
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PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
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PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
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}
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if (new_stack) {
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PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
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PUSHL(ssp, esp, sp_mask, ESP);
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}
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PUSHL(ssp, esp, sp_mask, compute_eflags());
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PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
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PUSHL(ssp, esp, sp_mask, old_eip);
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if (has_error_code) {
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PUSHL(ssp, esp, sp_mask, error_code);
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}
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} else {
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if (new_stack) {
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PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
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PUSHW(ssp, esp, sp_mask, ESP);
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}
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PUSHW(ssp, esp, sp_mask, compute_eflags());
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PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
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PUSHW(ssp, esp, sp_mask, old_eip);
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if (has_error_code) {
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PUSHW(ssp, esp, sp_mask, error_code);
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}
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}
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if (new_stack) {
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ss = (ss & ~3) | dpl;
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cpu_x86_load_seg_cache(env, R_SS, ss,
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ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
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}
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ESP = (ESP & ~sp_mask) | (esp & sp_mask);
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selector = (selector & ~3) | dpl;
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cpu_x86_load_seg_cache(env, R_CS, selector,
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get_seg_base(e1, e2),
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@ -699,56 +765,7 @@ static void do_interrupt_protected(int intno, int is_int, int error_code,
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e2);
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cpu_x86_set_cpl(env, dpl);
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env->eip = offset;
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ESP = esp - push_size;
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ssp = env->segs[R_SS].base + esp;
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if (shift == 1) {
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int old_eflags;
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if (env->eflags & VM_MASK) {
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ssp -= 4;
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stl_kernel(ssp, env->segs[R_GS].selector);
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ssp -= 4;
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stl_kernel(ssp, env->segs[R_FS].selector);
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ssp -= 4;
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stl_kernel(ssp, env->segs[R_DS].selector);
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ssp -= 4;
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stl_kernel(ssp, env->segs[R_ES].selector);
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}
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if (new_stack) {
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ssp -= 4;
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stl_kernel(ssp, old_ss);
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ssp -= 4;
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stl_kernel(ssp, old_esp);
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}
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ssp -= 4;
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old_eflags = compute_eflags();
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stl_kernel(ssp, old_eflags);
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ssp -= 4;
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stl_kernel(ssp, old_cs);
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ssp -= 4;
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stl_kernel(ssp, old_eip);
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if (has_error_code) {
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ssp -= 4;
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stl_kernel(ssp, error_code);
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}
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} else {
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if (new_stack) {
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ssp -= 2;
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stw_kernel(ssp, old_ss);
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ssp -= 2;
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stw_kernel(ssp, old_esp);
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}
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ssp -= 2;
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stw_kernel(ssp, compute_eflags());
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ssp -= 2;
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stw_kernel(ssp, old_cs);
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ssp -= 2;
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stw_kernel(ssp, old_eip);
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if (has_error_code) {
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ssp -= 2;
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stw_kernel(ssp, error_code);
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}
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}
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/* interrupt gate clear IF mask */
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if ((type & 1) == 0) {
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env->eflags &= ~IF_MASK;
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@ -780,12 +797,10 @@ static void do_interrupt_real(int intno, int is_int, int error_code,
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else
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old_eip = env->eip;
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old_cs = env->segs[R_CS].selector;
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esp -= 2;
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stw_kernel(ssp + (esp & 0xffff), compute_eflags());
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esp -= 2;
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stw_kernel(ssp + (esp & 0xffff), old_cs);
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esp -= 2;
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stw_kernel(ssp + (esp & 0xffff), old_eip);
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/* XXX: use SS segment size ? */
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PUSHW(ssp, esp, 0xffff, compute_eflags());
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PUSHW(ssp, esp, 0xffff, old_cs);
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PUSHW(ssp, esp, 0xffff, old_eip);
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/* update processor state */
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ESP = (ESP & ~0xffff) | (esp & 0xffff);
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@ -1247,26 +1262,17 @@ void helper_lcall_real_T0_T1(int shift, int next_eip)
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new_cs = T0;
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new_eip = T1;
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esp = ESP;
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esp_mask = 0xffffffff;
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if (!(env->segs[R_SS].flags & DESC_B_MASK))
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esp_mask = 0xffff;
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esp_mask = get_sp_mask(env->segs[R_SS].flags);
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ssp = env->segs[R_SS].base;
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if (shift) {
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esp -= 4;
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stl_kernel(ssp + (esp & esp_mask), env->segs[R_CS].selector);
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esp -= 4;
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stl_kernel(ssp + (esp & esp_mask), next_eip);
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PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
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PUSHL(ssp, esp, esp_mask, next_eip);
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} else {
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esp -= 2;
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stw_kernel(ssp + (esp & esp_mask), env->segs[R_CS].selector);
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esp -= 2;
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stw_kernel(ssp + (esp & esp_mask), next_eip);
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PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
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PUSHW(ssp, esp, esp_mask, next_eip);
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}
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if (!(env->segs[R_SS].flags & DESC_B_MASK))
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ESP = (ESP & ~0xffff) | (esp & 0xffff);
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else
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ESP = esp;
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ESP = (ESP & ~esp_mask) | (esp & esp_mask);
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env->eip = new_eip;
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env->segs[R_CS].selector = new_cs;
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env->segs[R_CS].base = (uint8_t *)(new_cs << 4);
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@ -1275,10 +1281,10 @@ void helper_lcall_real_T0_T1(int shift, int next_eip)
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/* protected mode call */
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void helper_lcall_protected_T0_T1(int shift, int next_eip)
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{
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int new_cs, new_eip;
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int new_cs, new_eip, new_stack, i;
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uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
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uint32_t ss, ss_e1, ss_e2, push_size, sp, type, ss_dpl;
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uint32_t old_ss, old_esp, val, i, limit;
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uint32_t ss, ss_e1, ss_e2, sp, type, ss_dpl, sp_mask;
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uint32_t val, limit, old_sp_mask;
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uint8_t *ssp, *old_ssp;
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new_cs = T0;
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@ -1319,30 +1325,21 @@ void helper_lcall_protected_T0_T1(int shift, int next_eip)
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raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
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sp = ESP;
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if (!(env->segs[R_SS].flags & DESC_B_MASK))
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sp &= 0xffff;
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ssp = env->segs[R_SS].base + sp;
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sp_mask = get_sp_mask(env->segs[R_SS].flags);
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ssp = env->segs[R_SS].base;
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if (shift) {
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ssp -= 4;
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stl_kernel(ssp, env->segs[R_CS].selector);
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ssp -= 4;
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stl_kernel(ssp, next_eip);
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PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
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PUSHL(ssp, sp, sp_mask, next_eip);
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} else {
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ssp -= 2;
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stw_kernel(ssp, env->segs[R_CS].selector);
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ssp -= 2;
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stw_kernel(ssp, next_eip);
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PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
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PUSHW(ssp, sp, sp_mask, next_eip);
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}
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sp -= (4 << shift);
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limit = get_seg_limit(e1, e2);
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if (new_eip > limit)
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raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
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/* from this point, not restartable */
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if (!(env->segs[R_SS].flags & DESC_B_MASK))
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ESP = (ESP & 0xffff0000) | (sp & 0xffff);
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else
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ESP = sp;
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ESP = (ESP & ~sp_mask) | (sp & sp_mask);
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cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
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get_seg_base(e1, e2), limit, e2);
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EIP = new_eip;
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@ -1413,77 +1410,63 @@ void helper_lcall_protected_T0_T1(int shift, int next_eip)
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if (!(ss_e2 & DESC_P_MASK))
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raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
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push_size = ((param_count * 2) + 8) << shift;
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// push_size = ((param_count * 2) + 8) << shift;
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old_esp = ESP;
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old_ss = env->segs[R_SS].selector;
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if (!(env->segs[R_SS].flags & DESC_B_MASK))
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old_esp &= 0xffff;
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old_ssp = env->segs[R_SS].base + old_esp;
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old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
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old_ssp = env->segs[R_SS].base;
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/* XXX: from this point not restartable */
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ss = (ss & ~3) | dpl;
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cpu_x86_load_seg_cache(env, R_SS, ss,
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get_seg_base(ss_e1, ss_e2),
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get_seg_limit(ss_e1, ss_e2),
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ss_e2);
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if (!(ss_e2 & DESC_B_MASK))
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sp &= 0xffff;
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ssp = env->segs[R_SS].base + sp;
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sp_mask = get_sp_mask(ss_e2);
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ssp = get_seg_base(ss_e1, ss_e2);
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if (shift) {
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ssp -= 4;
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stl_kernel(ssp, old_ss);
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ssp -= 4;
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stl_kernel(ssp, old_esp);
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ssp -= 4 * param_count;
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for(i = 0; i < param_count; i++) {
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val = ldl_kernel(old_ssp + i * 4);
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stl_kernel(ssp + i * 4, val);
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PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
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PUSHL(ssp, sp, sp_mask, ESP);
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for(i = param_count - 1; i >= 0; i--) {
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val = ldl_kernel(old_ssp + ((ESP + i * 4) & old_sp_mask));
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PUSHL(ssp, sp, sp_mask, val);
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}
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} else {
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ssp -= 2;
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stw_kernel(ssp, old_ss);
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ssp -= 2;
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stw_kernel(ssp, old_esp);
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ssp -= 2 * param_count;
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for(i = 0; i < param_count; i++) {
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val = lduw_kernel(old_ssp + i * 2);
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stw_kernel(ssp + i * 2, val);
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PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
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PUSHW(ssp, sp, sp_mask, ESP);
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for(i = param_count - 1; i >= 0; i--) {
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val = lduw_kernel(old_ssp + ((ESP + i * 2) & old_sp_mask));
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PUSHW(ssp, sp, sp_mask, val);
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}
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}
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new_stack = 1;
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} else {
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/* to same priviledge */
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if (!(env->segs[R_SS].flags & DESC_B_MASK))
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sp &= 0xffff;
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ssp = env->segs[R_SS].base + sp;
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push_size = (4 << shift);
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sp = ESP;
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sp_mask = get_sp_mask(env->segs[R_SS].flags);
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ssp = env->segs[R_SS].base;
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// push_size = (4 << shift);
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new_stack = 0;
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}
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if (shift) {
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ssp -= 4;
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stl_kernel(ssp, env->segs[R_CS].selector);
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ssp -= 4;
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stl_kernel(ssp, next_eip);
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PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
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PUSHL(ssp, sp, sp_mask, next_eip);
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} else {
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ssp -= 2;
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stw_kernel(ssp, env->segs[R_CS].selector);
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ssp -= 2;
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stw_kernel(ssp, next_eip);
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PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
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PUSHW(ssp, sp, sp_mask, next_eip);
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}
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/* from this point, not restartable */
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if (new_stack) {
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ss = (ss & ~3) | dpl;
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cpu_x86_load_seg_cache(env, R_SS, ss,
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ssp,
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get_seg_limit(ss_e1, ss_e2),
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ss_e2);
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}
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sp -= push_size;
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selector = (selector & ~3) | dpl;
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cpu_x86_load_seg_cache(env, R_CS, selector,
|
||||
get_seg_base(e1, e2),
|
||||
get_seg_limit(e1, e2),
|
||||
e2);
|
||||
cpu_x86_set_cpl(env, dpl);
|
||||
|
||||
if (!(env->segs[R_SS].flags & DESC_B_MASK))
|
||||
ESP = (ESP & 0xffff0000) | (sp & 0xffff);
|
||||
else
|
||||
ESP = sp;
|
||||
ESP = (ESP & ~sp_mask) | (sp & sp_mask);
|
||||
EIP = offset;
|
||||
}
|
||||
}
|
||||
|
|
@ -1491,26 +1474,26 @@ void helper_lcall_protected_T0_T1(int shift, int next_eip)
|
|||
/* real and vm86 mode iret */
|
||||
void helper_iret_real(int shift)
|
||||
{
|
||||
uint32_t sp, new_cs, new_eip, new_eflags, new_esp;
|
||||
uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
|
||||
uint8_t *ssp;
|
||||
int eflags_mask;
|
||||
|
||||
sp = ESP & 0xffff;
|
||||
ssp = env->segs[R_SS].base + sp;
|
||||
sp_mask = 0xffff; /* XXXX: use SS segment size ? */
|
||||
sp = ESP;
|
||||
ssp = env->segs[R_SS].base;
|
||||
if (shift == 1) {
|
||||
/* 32 bits */
|
||||
new_eflags = ldl_kernel(ssp + 8);
|
||||
new_cs = ldl_kernel(ssp + 4) & 0xffff;
|
||||
new_eip = ldl_kernel(ssp) & 0xffff;
|
||||
POPL(ssp, sp, sp_mask, new_eip);
|
||||
POPL(ssp, sp, sp_mask, new_cs);
|
||||
new_cs &= 0xffff;
|
||||
POPL(ssp, sp, sp_mask, new_eflags);
|
||||
} else {
|
||||
/* 16 bits */
|
||||
new_eflags = lduw_kernel(ssp + 4);
|
||||
new_cs = lduw_kernel(ssp + 2);
|
||||
new_eip = lduw_kernel(ssp);
|
||||
POPW(ssp, sp, sp_mask, new_eip);
|
||||
POPW(ssp, sp, sp_mask, new_cs);
|
||||
POPW(ssp, sp, sp_mask, new_eflags);
|
||||
}
|
||||
new_esp = sp + (6 << shift);
|
||||
ESP = (ESP & 0xffff0000) |
|
||||
(new_esp & 0xffff);
|
||||
ESP = (ESP & ~sp_mask) | (sp & 0xffff);
|
||||
load_seg_vm(R_CS, new_cs);
|
||||
env->eip = new_eip;
|
||||
if (env->eflags & VM_MASK)
|
||||
|
|
@ -1525,31 +1508,38 @@ void helper_iret_real(int shift)
|
|||
/* protected mode iret */
|
||||
static inline void helper_ret_protected(int shift, int is_iret, int addend)
|
||||
{
|
||||
uint32_t sp, new_cs, new_eip, new_eflags, new_esp, new_ss;
|
||||
uint32_t sp, new_cs, new_eip, new_eflags, new_esp, new_ss, sp_mask;
|
||||
uint32_t new_es, new_ds, new_fs, new_gs;
|
||||
uint32_t e1, e2, ss_e1, ss_e2;
|
||||
int cpl, dpl, rpl, eflags_mask;
|
||||
uint8_t *ssp;
|
||||
|
||||
sp_mask = get_sp_mask(env->segs[R_SS].flags);
|
||||
sp = ESP;
|
||||
if (!(env->segs[R_SS].flags & DESC_B_MASK))
|
||||
sp &= 0xffff;
|
||||
ssp = env->segs[R_SS].base + sp;
|
||||
ssp = env->segs[R_SS].base;
|
||||
if (shift == 1) {
|
||||
/* 32 bits */
|
||||
if (is_iret)
|
||||
new_eflags = ldl_kernel(ssp + 8);
|
||||
new_cs = ldl_kernel(ssp + 4) & 0xffff;
|
||||
new_eip = ldl_kernel(ssp);
|
||||
if (is_iret && (new_eflags & VM_MASK))
|
||||
goto return_to_vm86;
|
||||
POPL(ssp, sp, sp_mask, new_eip);
|
||||
POPL(ssp, sp, sp_mask, new_cs);
|
||||
new_cs &= 0xffff;
|
||||
if (is_iret) {
|
||||
POPL(ssp, sp, sp_mask, new_eflags);
|
||||
if (new_eflags & VM_MASK)
|
||||
goto return_to_vm86;
|
||||
}
|
||||
} else {
|
||||
/* 16 bits */
|
||||
POPW(ssp, sp, sp_mask, new_eip);
|
||||
POPW(ssp, sp, sp_mask, new_cs);
|
||||
if (is_iret)
|
||||
new_eflags = lduw_kernel(ssp + 4);
|
||||
new_cs = lduw_kernel(ssp + 2);
|
||||
new_eip = lduw_kernel(ssp);
|
||||
POPW(ssp, sp, sp_mask, new_eflags);
|
||||
}
|
||||
#ifdef DEBUG_PCALL
|
||||
if (loglevel) {
|
||||
fprintf(logfile, "lret new %04x:%08x\n",
|
||||
new_cs, new_eip);
|
||||
}
|
||||
#endif
|
||||
if ((new_cs & 0xfffc) == 0)
|
||||
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
|
||||
if (load_segment(&e1, &e2, new_cs) != 0)
|
||||
|
|
@ -1572,24 +1562,24 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend)
|
|||
if (!(e2 & DESC_P_MASK))
|
||||
raise_exception_err(EXCP0B_NOSEG, new_cs & 0xfffc);
|
||||
|
||||
sp += addend;
|
||||
if (rpl == cpl) {
|
||||
/* return to same priledge level */
|
||||
cpu_x86_load_seg_cache(env, R_CS, new_cs,
|
||||
get_seg_base(e1, e2),
|
||||
get_seg_limit(e1, e2),
|
||||
e2);
|
||||
new_esp = sp + (4 << shift) + ((2 * is_iret) << shift) + addend;
|
||||
} else {
|
||||
/* return to different priviledge level */
|
||||
ssp += (4 << shift) + ((2 * is_iret) << shift) + addend;
|
||||
if (shift == 1) {
|
||||
/* 32 bits */
|
||||
new_esp = ldl_kernel(ssp);
|
||||
new_ss = ldl_kernel(ssp + 4) & 0xffff;
|
||||
POPL(ssp, sp, sp_mask, new_esp);
|
||||
POPL(ssp, sp, sp_mask, new_ss);
|
||||
new_ss &= 0xffff;
|
||||
} else {
|
||||
/* 16 bits */
|
||||
new_esp = lduw_kernel(ssp);
|
||||
new_ss = lduw_kernel(ssp + 2);
|
||||
POPW(ssp, sp, sp_mask, new_esp);
|
||||
POPW(ssp, sp, sp_mask, new_ss);
|
||||
}
|
||||
|
||||
if ((new_ss & 3) != rpl)
|
||||
|
|
@ -1615,12 +1605,10 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend)
|
|||
get_seg_limit(ss_e1, ss_e2),
|
||||
ss_e2);
|
||||
cpu_x86_set_cpl(env, rpl);
|
||||
sp = new_esp;
|
||||
/* XXX: change sp_mask according to old segment ? */
|
||||
}
|
||||
if (env->segs[R_SS].flags & DESC_B_MASK)
|
||||
ESP = new_esp;
|
||||
else
|
||||
ESP = (ESP & 0xffff0000) |
|
||||
(new_esp & 0xffff);
|
||||
ESP = (ESP & ~sp_mask) | (sp & sp_mask);
|
||||
env->eip = new_eip;
|
||||
if (is_iret) {
|
||||
/* NOTE: 'cpl' can be different from the current CPL */
|
||||
|
|
@ -1635,22 +1623,22 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend)
|
|||
return;
|
||||
|
||||
return_to_vm86:
|
||||
new_esp = ldl_kernel(ssp + 12);
|
||||
new_ss = ldl_kernel(ssp + 16);
|
||||
new_es = ldl_kernel(ssp + 20);
|
||||
new_ds = ldl_kernel(ssp + 24);
|
||||
new_fs = ldl_kernel(ssp + 28);
|
||||
new_gs = ldl_kernel(ssp + 32);
|
||||
POPL(ssp, sp, sp_mask, new_esp);
|
||||
POPL(ssp, sp, sp_mask, new_ss);
|
||||
POPL(ssp, sp, sp_mask, new_es);
|
||||
POPL(ssp, sp, sp_mask, new_ds);
|
||||
POPL(ssp, sp, sp_mask, new_fs);
|
||||
POPL(ssp, sp, sp_mask, new_gs);
|
||||
|
||||
/* modify processor state */
|
||||
load_eflags(new_eflags, FL_UPDATE_CPL0_MASK | VM_MASK | VIF_MASK | VIP_MASK);
|
||||
load_seg_vm(R_CS, new_cs);
|
||||
load_seg_vm(R_CS, new_cs & 0xffff);
|
||||
cpu_x86_set_cpl(env, 3);
|
||||
load_seg_vm(R_SS, new_ss);
|
||||
load_seg_vm(R_ES, new_es);
|
||||
load_seg_vm(R_DS, new_ds);
|
||||
load_seg_vm(R_FS, new_fs);
|
||||
load_seg_vm(R_GS, new_gs);
|
||||
load_seg_vm(R_SS, new_ss & 0xffff);
|
||||
load_seg_vm(R_ES, new_es & 0xffff);
|
||||
load_seg_vm(R_DS, new_ds & 0xffff);
|
||||
load_seg_vm(R_FS, new_fs & 0xffff);
|
||||
load_seg_vm(R_GS, new_gs & 0xffff);
|
||||
|
||||
env->eip = new_eip;
|
||||
ESP = new_esp;
|
||||
|
|
|
|||
Loading…
Reference in New Issue