target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX
Note that the previous direct reference to reserve_val, - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val2) - : offsetof(CPUPPCState, reserve_val))); was incorrect because all references should have gone through cpu_reserve_val. Create a cpu_reserve_val2 tcg temp to fix this. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221112061122.2720163-2-richard.henderson@linaro.org>
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@ -818,6 +818,4 @@ DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG,
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void, env, tl, i64, i64, i32)
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DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG,
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void, env, tl, i64, i64, i32)
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DEF_HELPER_5(stqcx_le_parallel, i32, env, tl, i64, i64, i32)
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DEF_HELPER_5(stqcx_be_parallel, i32, env, tl, i64, i64, i32)
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#endif
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@ -413,50 +413,6 @@ void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr,
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val = int128_make128(lo, hi);
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cpu_atomic_sto_be_mmu(env, addr, val, opidx, GETPC());
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}
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uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t new_lo, uint64_t new_hi,
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uint32_t opidx)
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{
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bool success = false;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_CMPXCHG128);
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if (likely(addr == env->reserve_addr)) {
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Int128 oldv, cmpv, newv;
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cmpv = int128_make128(env->reserve_val2, env->reserve_val);
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newv = int128_make128(new_lo, new_hi);
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oldv = cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv,
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opidx, GETPC());
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success = int128_eq(oldv, cmpv);
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}
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env->reserve_addr = -1;
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return env->so + success * CRF_EQ_BIT;
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}
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uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
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uint64_t new_lo, uint64_t new_hi,
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uint32_t opidx)
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{
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bool success = false;
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/* We will have raised EXCP_ATOMIC from the translator. */
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assert(HAVE_CMPXCHG128);
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if (likely(addr == env->reserve_addr)) {
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Int128 oldv, cmpv, newv;
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cmpv = int128_make128(env->reserve_val2, env->reserve_val);
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newv = int128_make128(new_lo, new_hi);
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oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv,
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opidx, GETPC());
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success = int128_eq(oldv, cmpv);
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}
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env->reserve_addr = -1;
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return env->so + success * CRF_EQ_BIT;
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}
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#endif
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/*****************************************************************************/
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@ -72,6 +72,7 @@ static TCGv cpu_cfar;
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static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
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static TCGv cpu_reserve;
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static TCGv cpu_reserve_val;
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static TCGv cpu_reserve_val2;
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static TCGv cpu_fpscr;
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static TCGv_i32 cpu_access_type;
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@ -143,6 +144,9 @@ void ppc_translate_init(void)
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cpu_reserve_val = tcg_global_mem_new(cpu_env,
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offsetof(CPUPPCState, reserve_val),
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"reserve_val");
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cpu_reserve_val2 = tcg_global_mem_new(cpu_env,
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offsetof(CPUPPCState, reserve_val2),
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"reserve_val2");
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cpu_fpscr = tcg_global_mem_new(cpu_env,
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offsetof(CPUPPCState, fpscr), "fpscr");
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@ -3998,78 +4002,66 @@ static void gen_lqarx(DisasContext *ctx)
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/* stqcx. */
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static void gen_stqcx_(DisasContext *ctx)
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{
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TCGLabel *lab_fail, *lab_over;
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int rs = rS(ctx->opcode);
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TCGv EA, hi, lo;
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TCGv EA, t0, t1;
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TCGv_i128 cmp, val;
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if (unlikely(rs & 1)) {
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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return;
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}
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lab_fail = gen_new_label();
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lab_over = gen_new_label();
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gen_set_access_type(ctx, ACCESS_RES);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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/* Note that the low part is always in RS+1, even in LE mode. */
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lo = cpu_gpr[rs + 1];
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hi = cpu_gpr[rs];
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if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
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if (HAVE_CMPXCHG128) {
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TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN);
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if (ctx->le_mode) {
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gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
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EA, lo, hi, oi);
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} else {
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gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
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EA, lo, hi, oi);
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}
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tcg_temp_free_i32(oi);
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} else {
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/* Restart with exclusive lock. */
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gen_helper_exit_atomic(cpu_env);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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tcg_temp_free(EA);
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} else {
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TCGLabel *lab_fail = gen_new_label();
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TCGLabel *lab_over = gen_new_label();
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
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tcg_temp_free(EA);
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gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
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tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
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? offsetof(CPUPPCState, reserve_val2)
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: offsetof(CPUPPCState, reserve_val)));
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tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
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cmp = tcg_temp_new_i128();
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val = tcg_temp_new_i128();
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tcg_gen_addi_i64(t0, cpu_reserve, 8);
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gen_qemu_ld64_i64(ctx, t0, t0);
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tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
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? offsetof(CPUPPCState, reserve_val)
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: offsetof(CPUPPCState, reserve_val2)));
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tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
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tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val);
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/* Success */
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gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
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tcg_gen_addi_i64(t0, cpu_reserve, 8);
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gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
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/* Note that the low part is always in RS+1, even in LE mode. */
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tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]);
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tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx,
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DEF_MEMOP(MO_128 | MO_ALIGN));
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tcg_temp_free_i128(cmp);
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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tcg_gen_extr_i128_i64(t1, t0, val);
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tcg_temp_free_i128(val);
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tcg_gen_xor_tl(t1, t1, cpu_reserve_val2);
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tcg_gen_xor_tl(t0, t0, cpu_reserve_val);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_temp_free(t1);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0);
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tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
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tcg_gen_or_tl(t0, t0, cpu_so);
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tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
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tcg_temp_free(t0);
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tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
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tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
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tcg_gen_br(lab_over);
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gen_set_label(lab_fail);
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/*
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* Address mismatch implies failure. But we still need to provide
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* the memory barrier semantics of the instruction.
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*/
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
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gen_set_label(lab_over);
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tcg_gen_movi_tl(cpu_reserve, -1);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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}
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#endif /* defined(TARGET_PPC64) */
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